Advanced Packaging Makes Testing More Complex


The limits of monolithic integration, together with advances in chip interconnect and packaging technologies, have spurred the growth of heterogeneous advanced packaging where multiple dies are co-packaged using 2.5D and 3D approaches. But this also raises complex test challenges, which are driving new standards and approaches to advanced-package testing. While many of the showstopper issues... » read more

Week in Review: IoT, Security and Automotive


Internet of Things Western Digital Corp. and Codasip are working together on Western Digital’s SweRV Core EH1, which is a RISC-V core with a 32-bit, dual superscalar, 9-stage pipeline architecture. The core, launched earlier this is aimed at embedded devices supporting data-intensive edge applications, such as storage controllers, industrial IoT, real-time analytics in surveillance systems, ... » read more

The Week In Review: Manufacturing


Chipmakers AMD has entered into a long-term amendment to its wafer supply agreement (WSA) with GlobalFoundries for the period from Jan. 1, 2016 to Dec. 31, 2020. Today, GlobalFoundries’ Fab 8 in Malta, N.Y. is playing a big role in providing leading-edge foundry capacity for AMD's graphics and processor products. As part of the amended deal, AMD will grant to West Coast Hitech, a subsidia... » read more

Bulk CMOS Vs. FD-SOI


The leading edge of the chip market increasingly is divided over whether to move to finFETs or whether to stay at 28nm using different materials and potentially even advanced packaging. Decisions about which approach to take frequently boil down to performance, power, form factor, cost, and the maturity of the individual technologies. All of those can vary by market, by vendor and by process... » read more

Foundries Expand Their Scope


By Ed Sperling & Mark LaPedus Major foundries are stepping up their offerings across a wide swath of technology nodes, specialty processes and advanced packaging—a recognition that end markets are fragmenting and that the path forward includes a mix of new and established processes. As the smart phone market flattens, there is no single "next big thing" to drive volume at the most ... » read more

Brite Semiconductor: Design Services


These days it's increasingly common for large commercial foundries to have a design services counterpart—TSMC has GlobalUnichip. GlobalFoundries has an entire ecosystem as well as a dedicated partner, Invecas. And China's SMIC has Brite Semiconductor. Brite was founded in 2008 by Open-Silicon as a way to tap the Chinese market, but the startup has taken some twists since then. It now is un... » read more

Custom Versus Platform Design


The increase in [getkc id="81" kc_name="SoC"] complexity is being mirrored by a rise in complexity within the markets that drive demand for those chips. The upshot is that a push toward greater connectivity, lower power and better performance—and all for a minimal cost—has turned the pros and cons for custom design vs. platforms and superchips into a murky decision-making process. For t... » read more

The Week In Review: Design


IP Cadence rolled out a portfolio of stacked die memory verification IP to support Wide I/O-2, Hybrid Memory Cube, high-bandwidth memory, and DDR4-3DS. Included are direct memory access for read, write, save, preload and comparison of memory contents, assertions, error configurability, and a built-in address manager. ARM rolled out additions to its enterprise-class SoC interconnects for qua... » read more

The Week In Review: Design


Tools Mentor Graphics announced its Enterprise Verification Platform (EVP) that pulls together the company’s Questa verification technologies with Veloce OS3 global emulation resourcing technology, and the Visualizer debug technology into what it says is a globally accessible, high-performance datacenter resource. The system is aimed at global resource management and supports project teams a... » read more

The Week In Review: July 15


By Mark LaPedus There are more problems surfacing with extreme ultraviolet (EUV) lithography. Yes, the light source remains a problem, but the resists appear to be in decent shape. “The next challenge is the mask blank,” said Stefan Wurm, director of Sematech’s lithography program. The new problem involves ion beam deposition, which apparently is causing defects and overfill on EUV masks... » read more

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