The Week In Review: July 15

By Mark LaPedus - 15 Jul, 2013 - Comments: 0

By Mark LaPedus There are more problems surfacing with extreme ultraviolet (EUV) lithography. Yes, the light source remains a problem, but the resists appear to be in decent shape. “The next challenge is the mask blank,” said Stefan Wurm, director of Sematech’s lithography program. The new problem involves ion beam deposition, which apparently is causing defects and overfill on EUV masks... » read more

The Week In Review: July 12

By Ed Sperling - 12 Jul, 2013 - Comments: 0

By Ed Sperling Cadence rolled a new version of its layout suite of tools for electrically aware designs, allowing design teams to check on electrical issues while the layout is being done. The company says this can reduce circuit design time by up to 30%, in addition to optimizing for performance and area. Cadence also announced a deal with Global Unichip, which successfully taped out a 20nm ... » read more

Who Owns What And Why

By Ed Sperling - 23 Aug, 2012 - Comments: 0

Who’s calling the shots these days—and how long they’ll continue calling the shots—is turning out to be as much conjecture as playing the futures exchange. There are so many changes underway that even engineers are crossing boundaries no one ever expected and ending up in companies outside of IC design or moving from seemingly far afield into the design world. Still, there are some c... » read more

Who’s In Control?

By Ed Sperling - 26 May, 2011 - Comments: 0

By Ed Sperling A power shift is under way across the SoC world that ultimately determine who wins the business, who gets the biggest share and what technologies are ultimately used to get there. Complexity has reached a point where being able to pull the necessary pieces from a disaggregated supply chain is becoming much more difficult. That helps explain why all three of the major EDA comp... » read more

The Quest For A Better IP Integration Methodology

By Ed Sperling - 31 Mar, 2011 - Comments: 0

By Ed Sperling With the amount of IP in SoC designs now hitting an estimated 70% to 90%, companies are scrambling to figure out a way to more consistently integrate that IP and to test that it will work as expected. This is easier said than done, however, for a number of reasons: There are numerous types of IP, ranging from I/O to logic and memory. Not all IP is of equal quality. ... » read more

Journey To The Center Of The Ecosystem

By Ed Sperling - 14 Jan, 2010 - Comments: 0

From the outside it looks like business as usual, but the race for board seats on the GSA has become particularly competitive this year. GSA originally was created as an organization for fabless companies, but you wouldn’t know that looking at its membership roster. It has evolved into a who’s who of the entire semiconductor supply chain, including everyone from foundries like TSMC and... » read more

Outsourcing’s New Face

By Ed Sperling - 29 Oct, 2009 - Comments: 0

By Ed Sperling As the semiconductor industry digs out from one of the worst downturns in decades, the business of semiconductor design and engineering is changing. While the architecture and features are still being developed by chip companies, the actual work of developing the chip increasingly is being done by third parties. Outsourcing is hardly new concept in business. In the early pa... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer