The Week In Review: July 15

More EUV problems; CapEx picture; mixed forecasts; epi apps; Soitec expands; EDA tools.

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By Mark LaPedus
There are more problems surfacing with extreme ultraviolet (EUV) lithography. Yes, the light source remains a problem, but the resists appear to be in decent shape. “The next challenge is the mask blank,” said Stefan Wurm, director of Sematech’s lithography program. The new problem involves ion beam deposition, which apparently is causing defects and overfill on EUV masks, Wurm said. Work is under way to fix the problem.

There are some mixed signals in terms of semi CapEx right now. “We expect TSMC to raise its CapEx budget once more this year, Intel to lower CapEx once more this year, and Samsung to remain in CapEx limbo. The reality is that equipment demand is very fluid, and visibility remains low,” said Weston Twigg, an analyst with Pacific Crest Securities, in a research note.

Based on the various forecasts for semiconductor equipment, the mood was mixed at last week’s Semicon West trade show in San Francisco.

At a meeting of the company’s top investors and equity analysts, Applied Materials demonstrated plans to drive profitable growth across a number of market segments ranging from 3D NAND to new materials to inspection equipment.

For years—decades, in fact—the NMOS transistor world has been on cruise control. Not anymore.

Applied Materials is expanding its efforts in epitaxial technology with a newly developed NMOS transistor application for its Centura RP Epi system. This capability supports the industry’s move to extend epi deposition from PMOS transistors to NMOS transistors at the 20nm node, enabling chipmakers to build faster devices.

Applied Materials announced a suite of new defect review and classification technologies for its SEMVision family of products to accelerate time to yield for leading-edge chip manufacturing at 1X-nm and beyond.

Silicon-on-insulator (SOI) substrate specialist Soitec is in the midst of a expansion and diversification strategy as part a major effort to look for new and high-growth markets.

In the supply chain front, Shin‐Etsu Handotai (SEH) says it’s meeting the specs for FD-SOI wafers, and can quickly expand capacity to meet rising demand.

Soitec announced at the Semicon West trade show that its SOI technologies are now mainstream for manufacturing switches and antenna-tuners, key RF components used in all cell phones and tablet computers.

Soitec has completed its first solar power plant in California with modules from its new San Diego manufacturing facility.

Realtek Semiconductor is now using Mentor Graphics’ Calibre PERC product as its production signoff tool for performing sophisticated electrical circuit checks (ERC) on its designs.

Cadence Design Systems introduced a new approach to custom design with its Virtuoso Layout Suite for Electrically Aware Design (EAD).

Global Unichip has utilized Cadence’s Encounter Digital Implementation System (EDI) and the Litho Physical Analyzer to complete the tapeout of a 20nm system-on-a-chip (SoC) test chip.

TSMC has expanded collaboration with Cadence on the Virtuoso custom and analog design platform. Additionally, TSMC has extended its native SKILL-based process design kits (PDKs) portfolio to 16nm.

Sematech announced that Air Products has joined its front-end processes program. Air Products will work with Sematech to assess advanced materials and technologies for the development of sub-10nm node III-V devices.

Exar has acquired Cadeka Microcircuits. The transaction includes $29.0 million in initial consideration to be paid in a combination of cash and stock.