Chip Industry Week In Review


Amkor will provide turnkey advanced packaging and test services to TSMC in Amkor's planned facility in Peoria, Arizona, in a deal announced on Thursday. The companies jointly specified the packaging technologies, such as TSMC’s Integrated Fan-Out (InFO) and Chip on Wafer on Substrate (CoWoS). President Biden signed into law a bill that exempts some semiconductor projects funded by the U.S.... » read more

Why Chiplets Are So Critical In Automotive


Chiplets are gaining renewed attention in the automotive market, where increasing electrification and intense competition are forcing companies to accelerate their design and production schedules. Electrification has lit a fire under some of the biggest and best-known carmakers, which are struggling to remain competitive in the face of very short market windows and constantly changing requir... » read more

Using Keysight Design Data Management SOS In The Cloud


Integrated circuits (ICs) are becoming increasingly complex and resource intensive. This is challenging companies to design chips more efficiently and reduce the overall impact of peak processing loads. Companies typically use large server farms and high-performance storage systems to design and validate chips quickly and efficiently. However, this approach is very resource intensive. For ex... » read more

Chip Industry Week In Review


By Susan Rambo, Liz Allan, and Gregory Haley. TSMC rolled out the second version of its 3Dblox, which creates an infrastructure for stacking chiplets and other necessary components in a package, along with a standardized way of achieving that. Two novel features are chiplet mirroring for design reuse, and what is basically sandbox for power and thermal analysis of different design elements. ... » read more

Chip Industry Week In Review


By Liz Allan, Jesse Allen, and Karen Heyman Global semiconductor equipment billings dipped 2% year-over-year to US$25.8 billion in Q2, and slipped 4% compared with Q1, according to SEMI. Similarly, the top 10 semiconductor foundries reported a 1.1% quarterly-over-quarter revenue decline in Q2. A rebound is anticipated in Q3, according to TrendForce. Synopsys extended its AI-driven EDA ... » read more

Week In Review: Auto, Security, Pervasive Computing


The U.S. Department of Energy (DOE) announced $15.5 billion in funding and loans for retooling existing automotive factories for the transition to electric vehicles (EVs) and supporting local jobs, plus a notice of intent for $3.5 billion in funding to expand domestic manufacturing of batteries for EVs and the nation’s grid, and for battery materials and components that are currently imported... » read more

Week In Review: Design, Low Power


Arm is helping to address the ongoing talent shortage through its newly announced Semiconductor Education Alliance, with a long list of partners, including Arduino, Cadence, Cornell University, Semiconductor Research Corp., STMicroelectronics,Synopsys, Taiwan Semiconductor Research Institute, the All-India Council for Technical Education, and the University of Southampton. The Alliance... » read more

Week In Review: Auto, Security, Pervasive Computing


Pervasive computing Renesas introduced a narrowband Internet of Things (NB-IoT) chipset and dev kit for the Indian market. The LTE NB-IoT modem chipset, the RH1NS200, was designed for Indian telecommunications carriers by targeting bands 1,3, 5 and 8 and by following India’s carrier-approved LTE protocol stack and software suite. Low power usage is built in — it has a low Power Saving Mode... » read more

Considering The Power Of The Cloud For EDA


By Michael White, Siemens EDA, in technical collaboration with Peeyush Tugnawat, Google Cloud, and Philip Steinke, AMD At DAC 2022, Google Cloud, AMD, and Calibre Design Solutions presented an EDA in the cloud solution that enables companies to access virtually unlimited compute resources when and as needed to optimize their design and verification flows. If your company is considering addin... » read more

Week In Review: Design, Low Power


Cadence unveiled a new environment to automate and accelerate the complete design closure cycle from signoff optimization through routing, static timing analysis (STA), and extraction. The Certus Closure Solution allows concurrent, full-chip optimization through a massively parallel and distributed architecture and engine shared with Cadence’s Innovus Implementation System and the Tempus Timi... » read more

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