Failure To Launch


Failure analysis (FA) is an essential step for achieving sufficient yield in semiconductor manufacturing, but it’s struggling to keep pace with smaller dimensions, advanced packaging, and new power delivery architectures. All of these developments make defects harder to find and more expensive to fix, which impacts the reliability of chips and systems. Traditional failure analysis techniqu... » read more

Chip Industry Technical Paper Roundup: Feb. 25


New technical papers recently added to Semiconductor Engineering’s library: [table id=408 /] Find all technical papers here. » read more

Cradle-To-Grave Analysis Of The Carbon Footprint of AI Hardware (Google)


A new technical paper titled "Life-Cycle Emissions of AI Hardware: A Cradle-To-Grave Approach and Generational Trends" was published by researchers at Google. Abstract "Specialized hardware accelerators aid the rapid advancement of artificial intelligence (AI), and their efficiency impacts AI's environmental sustainability. This study presents the first publication of a comprehensive AI acc... » read more

Chip Industry Week In Review


The chip industry is well on its way to hit $1 trillion in revenue by the end of its decade. Several analyst firms released 2024 annual results and 2025 predictions: Worldwide semiconductor revenue reached $626 billion in 2024, an 18% increase versus 2023, according to preliminary Gartner report. Memory revenue grew about 70%  2024 versus 2023. The firm forecasts that HBM will make up 19%... » read more

Chip Industry Technical Paper Roundup: Jan. 20


New technical papers recently added to Semiconductor Engineering’s library: [table id=398 /] Find all technical papers here. » read more

AI Accelerators for Homomorphic Encryption Workloads


A new technical paper titled "Leveraging ASIC AI Chips for Homomorphic Encryption" was published by researchers at Georgia Tech, MIT, Google and Cornell University. Abstract: "Cloud-based services are making the outsourcing of sensitive client data increasingly common. Although homomorphic encryption (HE) offers strong privacy guarantee, it requires substantially more resources than compu... » read more

How Google And Intel Use Calibre DesignEnhancer To Reduce IR Drop And Improve Reliability


In the fast-paced world of semiconductor design, achieving both Design Rule Check (DRC) clean layouts and optimal electrical performance is crucial for minimizing design iterations, reducing time-to-market and ensuring product reliability. This paper explores how the Calibre DesignEnhancer (DE) analysis-based, signoff-quality EMIR solution helps design teams meet these challenges by enhancing p... » read more

Chip Industry Week in Review


Lawrence Livermore National Laboratory is ramping up R&D for next-gen EUV and plasma-based particle sources, aiming to increase the EUV laser source power by an order of magnitude while also making it more energy-efficient. Specifically, the goal is to replace today's CO2-based laser with a solid-state laser, using a thulium-doped yttrium lithium fluoride medium to increase the laser's powe... » read more

Chip Industry Week In Review


The 2024 IEEE International Electron Devices Meeting (IEDM) was held this week, prompting a number of announcements from: imec: Proposed a new CFET-based standard cell architecture for the A7 node containing two rows of CFETs with a shared signal routing wall in between, allowing standard cell heights to be reduced from 4 to 3.5T, compared to single-row CFETs. Integrated indium pho... » read more

FOPLP Gains Traction in Advanced Semiconductor Packaging


Fan-Out Panel-Level Packaging (FOPLP) for advanced nodes, once hindered by manufacturability and yield challenges, is emerging as a promising solution to meet the industry’s demands for higher integration densities and cost efficiency. Traditionally, FOPLP has been a go-to solution for cost-sensitive applications in consumer electronics, IoT devices, and mid-tier automotive systems. Its ab... » read more

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