tag: heat

Fostering Thermal Design Innovation Using Chip-Package-System Analysis Techniques
By Ansys - 16 Jul, 2018 - Comments: 0

As devices continue to become smaller and more portable Moore’s Law continues to increase the number of transistors that fit within a chip albeit many predict an end to this in the near future. However new interconnect technologies that use Through-Silicon-Vias (TSVs) can place ICs next to each other using 2.5D Interposers or stack chips in 3D resulting in even greater system scaling. This co... » read more

Power/Performance Bits: July 16
By Jesse Allen - 16 Jul, 2018 - Comments: 0

Bacterial solar Researchers at the University of British Columbia developed a solar cell that uses bacteria to convert light to energy. The cell worked as efficiently in dim light as in bright light, making solar a potential option in areas of the world that frequently have overcast skies. Called biogenic cells, they work by utilizing the natural dye that bacteria use for photosynthesis. Pr... » read more

System-Level Power Modeling Takes Root
By Ann Mutschler - 10 May, 2018 - Comments: 0

Power, heat, and their combined effects on aging and reliability, are becoming increasingly critical variables in the design of chips that will be used across a variety of new and existing markets. As more processing moves to edge, where sensors are generating a tsunami of data, there are a number of factors that need to be considered in designs. On one side, power budgets need to reflect th... » read more

IP And Power
By Brian Bailey - 08 Mar, 2018 - Comments: 0

[getkc id="108" kc_name="Power"] is quickly becoming a major differentiator for products, regardless of whether they are connected to a wall outlet or dependent on a battery. At the same time, increasing amounts of a chips content comes from third-party [getkc id="43" kc_name="IP"]. So how do system designers ensure that the complete system has an optimal power profile, and what can they do to ... » read more

Closing The Loop On Power Optimization
By Brian Bailey - 11 May, 2017 - Comments: 2

[getkc id="108" kc_name="Power"] has become a significant limiter for the capabilities of a chip at finer geometries, and making sure that performance is maximized for a given amount of power is becoming a critical design issue. But that is easier said than done, and the tools and methodologies to overcome the limitations of power are still in the early definition stages. The problem spans a... » read more

Power/Performance Bits: April 18
By Jesse Allen - 18 Apr, 2017 - Comments: 0

Cooling hotspots Engineers at Duke University and Intel developed a technology to cool hotspots in high-performance electronics. The new technology relies on a vapor chamber made of a super-hydrophobic floor with a sponge-like ceiling. When placed beneath operating electronics, moisture trapped in the ceiling vaporizes beneath emerging hotspots. The vapor escapes toward the floor, taking hea... » read more

Multi-Patterning Issues At 7nm, 5nm
By Ed Sperling - 28 Nov, 2016 - Comments: 13

Continuing to rely on 193nm immersion lithography with multiple patterning is becoming much more difficult at 7nm and 5nm. With the help of various resolution enhancement techniques, optical lithography using a deep ultraviolet excimer laser has been the workhorse patterning technology in the fab since the early 1980s. It is so closely tied with the continuation of [getkc id="74" comment="Mo... » read more

Controlling Heat
By Ann Mutschler - 12 Sep, 2016 - Comments: 0

Modeling on-chip thermal characteristics and chip-package interactions is becoming much more critical for advanced designs, but how to get there isn't always clear. Every chip, based on its target application, has a thermal design power (TDP) target. This is the typical power it can consume without overreaching the acceptable thermal limits in its intended environment. But in order to rate t... » read more

Tech Talk: Power Signoff
By Ed Sperling - 08 Sep, 2016 - Comments: 0

Ansys' Aveek Sarkar the challenges of power signoff at advanced process nodes, the impact of over-design, and what's necessary for sufficient coverage. [youtube vid=VQoT2KYW-AM] » read more

No More Straight Lines
By Ed Sperling - 12 May, 2016 - Comments: 0

Shrinking features on a chip is no longer the only way forward, and in an increasing number of designs and markets, it is no longer the best way forward. Power and performance are generally better dealt with using different architectures and microarchitectures, and all of those provide the potential to reduce silicon area (cost). Cramming more transistors on a die and working around leakage... » read more

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