tag: heterogeneous integration

Energy-Efficient Scalable Silicon Photonic Platform For AI Accelerator HW
By Technical Paper Link - 12 Mar, 2025 - Comments: 0

A new technical paper titled "Large-Scale Integrated Photonic Device Platform for Energy-Efficient AI/ML Accelerators" was published by researchers at HP Labs, IIT Madras, Microsoft Research and University of Michigan. Abstract "The convergence of deep learning and Big Data has spurred significant interest in developing novel hardware that can run large artificial intelligence (AI) workload... » read more

Low-Temperature Solid-Liquid Interdiffusion Bonding For High-Density Interconnect Applications
By Technical Paper Link - 19 Feb, 2025 - Comments: 0

A new technical paper titled "Facilitating Small-Pitch Interconnects with Low-Temperature Solid-Liquid Interdiffusion Bonding" was published by researchers at Aalto University in Finland. Abstract "The trend for 3D heterogeneous integration drives the need for a low-temperature bonding process for high-density interconnects (HDI). The Cu-Sn-In based solid-liquid interdiffusion (SLID) is a p... » read more

FOWLP Warpage: Review Of Causes, Modeling And Methodologies For Controlling
By Technical Paper Link - 14 Feb, 2025 - Comments: 0

A new technical paper titled "Warpage in wafer-level packaging: a review of causes, modelling, and mitigation strategies" was published by researchers at Arizona State University. Abstract "Wafer-level packaging (WLP) is a pivotal semiconductor packaging technology that enables heterogeneously integrated advanced semiconductor packages with high-density electrical interconnections through i... » read more

Power Delivery Challenges in 3D HI CIM Architectures for AI Accelerators (Georgia Tech)
By Technical Paper Link - 07 Feb, 2025 - Comments: 0

A new technical paper titled "Co-Optimization of Power Delivery Network Design for 3D Heterogeneous Integration of RRAM-based Compute In-Memory Accelerators" was published by researchers at Georgia Tech. Abstract: "3D heterogeneous integration (3D HI) offers promising solutions for incorporating substantial embedded memory into cutting-edge analog compute-in-memory (CIM) AI accelerators, ad... » read more

Optimization of Oxygen Plasma Conditions for Cu-Cu Bonding
By Technical Paper Link - 04 Feb, 2025 - Comments: 0

A new technical paper titled "Understanding and Optimizing Oxygen Plasma Treatment for Enhanced Cu-Cu Bonding Application" was published by researchers at Seoul National University of Science and Technology. Abstract "This study investigates the optimization of O2 plasma treatment conditions to enhance Cu-Cu bonding. The O2 plasma treatment conditions were optimized using Design of Experime... » read more

Assembly Design Rules Slowly Emerge
By Bryon Moyer - 27 Jan, 2025 - Comments: 0

Process design kits (PDKs) play an essential in ensuring that silicon technology can proceed from one generation to the next in a manner that design tools can keep up with. No such infrastructure has been needed for packaging in the past, but that's beginning to change with advanced packages. Heterogeneous assemblies are still ramping up, but their benefits are attracting new designs. “Chi... » read more

DFT At The Leading Edge
By Gregory Haley - 14 Jan, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss the rapidly changing landscape of design for testability (DFT), focusing on the impact of advancements in fault models, high-speed interfaces, and lifecycle data analytics, with Jeorge Hurtarte, senior director of product marketing in the Semiconductor Test Group at Teradyne; Sri Ganta, director of test products at Synopsys; D... » read more

Innovate Faster with A Multi-Die Solution
By Synopsys - 13 Nov, 2024 - Comments: 0

The semiconductor industry is experiencing a monumental shift in chip design, driven by the dramatic increase in AI compute performance requirements and limitations of Moore’s Law. The industry is adopting multi-die designs, which is the heterogeneous or homogeneous integration of dies (also called chiplets) in a single package. While multi-die design is the solution, it also introduces se... » read more

Big Changes Ahead For Analog Design
By Ed Sperling - 06 Nov, 2024 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss the impact of heterogeneous integration on in-house analog tools, and how that is changing the design process, with Mo Faisal, president and CEO of Movellus; Hany Elhak, executive director of product management at Synopsys; Cedric Pujol, product manager at Keysight; and Pradeep Thiagarajan, principal product manager for custom ... » read more

Advanced Packaging Driving New Collaboration Across Supply Chain
By Gregory Haley - 24 Oct, 2024 - Comments: 0

The semiconductor industry is undergoing a profound shift in packaging technologies to ones that rely on close collaboration among multiple stakeholders to solve intricate, multi-faceted, and extraordinarily complex problems. At the heart of this change is the convergence of heterogeneous integration, chiplets, and 3D stacking. Heterogeneous approaches allow companies to combine different te... » read more

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