Multicore Debug Evolves To The System-Level

By Ann Mutschler - 22 Dec, 2020 - Comments: 0

The proliferation and expansion of multicore architectures is making debug much more difficult and time-consuming, which in turn is increasing demand for more comprehensive system-level tools and approaches. Multicore/multiprocessor designs are the most complex devices to debug. More interactions and interdependencies between cores mean more things possibly can go wrong. In fact, so many pro... » read more

Pushing Performance: Analysis and Optimization of Multicore Communication with SLX

By Silexica - 29 May, 2019 - Comments: 0

In theory, multicore programming should be simple: Tasks are placed on available cores and allocated a data buffer in the shared memory to communicate data between two tasks. However, the amount of communication resources in the latest multicore SoC is very limited. One cannot deal with all the data communications required by all the tasks without being able to understand communication conte... » read more

The Rise Of Complex Debug On Heterogeneous Multicore SoCs

By Kathy Tufto - 25 Aug, 2016 - Comments: 0

When projects move away from discrete development of loosely coupled systems to an integrated heterogeneous environment, elephantine debugging challenges are created. These challenges do not exist during discrete development because developers are able to design, develop, test, and optimize within the confines of their own device. But when consolidating heterogeneous systems, developers and ... » read more

Not All Workloads Are Equal

By Chris Shore - 16 Jun, 2015 - Comments: 0

ARM's Ben and Otilia put a human face big on processing — who sleeps, who works, when they do each, and and what's behind their decision. Check out the video: [youtube vid=J2z7P9JKukc] big.LITTLE uses a heterogeneous multi-core approach to power optimization, where high-performance CPU cores are combined with the most efficient CPU cores to deliver peak-performance capacity, higher s... » read more

The Interconnect Bottleneck

By Ann Mutschler - 28 May, 2015 - Comments: 0

With communications playing a crucial role in the design and performance of multi-core SoCs, various interconnect structures have been proposed as promising solutions to simplify and optimize SoC design. However, sometimes things don’t go as planned and the interconnect becomes the bottleneck. “Under high utilization cases the DRAM will be over-constrained with requests from all the a... » read more

Addressing Design Challenges In Heterogeneous Multicore Embedded Systems

By Mentor, a Siemens Business - 27 May, 2015 - Comments: 0

Single-core processor designs for purpose-built devices used to rule the day. Now, heterogeneous multicore systems are quickly becoming the de facto architecture as devices are tasked to do more complex functions faster and more efficiently. In this paper, we’ll explore why hetero/multicore systems have become so popular and why many of our current procedures and practices must change if we a... » read more

The Week In Review: Design

By Ed Sperling - 17 Jul, 2014 - Comments: 0

Tools Cadence unveiled two new tools. The first is a rapid prototyping platform that the company claims will shorten bring-up time by 70%, with 4X improvements in capacity, with IEEE 1801 support for low-power verification through its emulation platform. The second is a single and multi-corner custom/analog extraction tool, which it claims will improve performance by 5X. The tool has been cert... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer