tag: HLS

Challenges In Using HLS For FPGA Design
By Loren Hobbs - 29 Apr, 2019 - Comments: 0

High-level synthesis (HLS) tools, which transform C/C++ source code to Verilog/VHDL, have been commercially available for over 15 years. HLS tools from FPGA vendors and EDA companies promise improved productivity through a higher-level of abstraction, faster verification and quicker design iterations. For example, simulating your design in C/C++ can be 10 to 100x faster than simulating in RTL (... » read more

Finding Code Problems Before High-Level Synthesis
By Mentor, a Siemens Business - 10 Apr, 2019 - Comments: 0

In order to significantly speed up verification and to handle complex algorithms that change daily, many companies are turning to a High-Level Synthesis (HLS) methodology. But, it is extremely important that the high-level C++ model is correct. In addition, the C++ language has ambiguities that can be tough to catch during simulation. Even if correctly written, the high-level model could be cod... » read more

Closing Functional And Structural Coverage On RTL Generated By High-Level Synthesis
By Mentor, a Siemens Business - 14 Mar, 2019 - Comments: 0

Most hardware design teams have a verification methodology that requires a deep understanding of the RTL to reach their verification goals, but this type of methodology is difficult to apply to the machine generated RTL from High-level Synthesis (HLS). This paper describes innovative techniques to use with existing methodologies, for example the Universal Verification Methodology (UVM), to clos... » read more

Smoke Testing A High-Level Synthesis Design
By Mentor, a Siemens Business - 27 Feb, 2019 - Comments: 0

Designing hardware using C++ and C++ testbenches brings orders of magnitude speed-up to simulation. But after High-Level Synthesis (HLS), teams need a way to quickly ensure that the newly-generated RTL is functionally the same as the original untimed C++. They don’t want to create an RTL testbench in order to make this comparison. What teams need is an automated smoke test to quickly make the... » read more

The Impact of Moore’s Law Ending
By Brian Bailey - 29 Oct, 2018 - Comments: 2

Over the past couple of process nodes the chip industry has come to grips with the fact that Moore's Law is slowing down or ending for many market segments. What isn't clear is what comes next, because even if chipmakers stay at older nodes they will face a series of new challenges that will drive up costs and increase design complexity. Chip design has faced a number of hurdles just to get ... » read more

Power Reduction In A Constrained World
By Rob Knoth - 09 Aug, 2018 - Comments: 0

Back when 40-28nm were new, leakage power for wireless designs dominated the optimization technology focus. This led to multiple VT optimization and power intent management for digital designs to minimize or shut off leakage. As wireless devices moved to FinFET nodes, dynamic power became dominant. As a result, optimization technology focus shifted to build up dynamic techniques to complement y... » read more

Synthesizing Computer Vision Designs To Hardware
By Mike Fingeroff - 26 Jul, 2018 - Comments: 0

Computer vision is one of the hottest markets in electronic design today. Digital processing of images and video with complex algorithms in order to interpret meaning has almost as many applications and markets as there are uses for the human eye. The biggest problem that designers face is that the computer vision system requirements and algorithms change quickly and often. Even the targ... » read more

Accelerate Computer Vision Design Using High-Level Synthesis
By Mentor, a Siemens Business - 25 Jul, 2018 - Comments: 0

Computer vision solutions are all around us, in cars, consumer products, security, retail, and agriculture. But, designing these solutions is not easy, mainly because of constant algorithm upgrades and related requirements changes. This means that wherever the team is in the RTL creation and verification flow, they might have to start over, which can cause an unacceptable delay in the productio... » read more

Could Liquid IP Lead To Better Chips?
By Brian Bailey - 13 Dec, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss the benefits that could come from making IP available as abstract blocks instead of RTL implementations with Mark Johnstone, technical director for Electronic Design Automation for [getentity id="22499" e_name="NXP"] Semiconductor; [getperson id="11489" p_name="Drew Wingard"], CTO at [getentity id="22605" e_name="Sonics"]; Bryan Bowyer, director of ... » read more

The 5G Design Dilemma
By Dave Pursley - 09 Nov, 2017 - Comments: 0

Nothing says low power and high performance like an emerging wireless standard that promises to increase link bandwidth, latency, and overall capacity by orders of magnitude while also reducing power. That emerging standard, of course, is 5G. With the number of devices that are projected to use 5G, it’s no surprise that 5G is a strategic initiative for many companies. This explains why des... » read more

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