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What Causes Semiconductor Aging?


Semiconductor technology has evolved to the point where no one can assume chips will last forever. If not carefully considered, aging can shorten the life of an IC below the needs for an intended application. Aging is well studied in technology circles, but while others less directly involved may understand at a general level this is a problem, it's not always obvious why. So what exactly ar... » read more

Reliability Concerns Shift Left Into Chip Design


Demand for lower defect rates and higher yields is increasing, in part because chips are now being used for safety- and mission-critical applications, and in part because it's a way of offsetting rising design and manufacturing costs. What's changed is the new emphasis on solving these problems in the initial design. In the past, defectivity and yield were considered problems for the fab. Re... » read more

Will Monolithic 3D DRAM Happen?


As DRAM scaling slows, the industry will need to look for other ways to keep pushing for more and cheaper bits of memory. The most common way of escaping the limits of planar scaling is to add the third dimension to the architecture. There are two ways to accomplish that. One is in a package, which is already happening. The second is to sale the die into the Z axis, which which has been a to... » read more

Replacement Gate High-k/Metal Gate nMOSFETs Using A Self-Aligned Halo-Compensated Channel Implant


A device design technique for boosting output resistance (Rout) characteristics of long-channel halo-doped nMOSFETs for replacement gate (RMG) high-k/metal gate (HK/MG) devices is proposed based on numerical simulations. We show that the self-aligned halo-compensated channel implant (HCCI) that is carried out after dummy poly gate removal provides compensation for the conventional halo doping. ... » read more

Aging Analysis Common Model Interface Gains Momentum


By Greg Curtis, Ahmed Ramadan, Ninad Pimparkar, and Jung-Suk Goo In February 2019, Siemens EDA wrote an article1 entitled “The Time Is Now for a Common Model Interface”. Since that time, we have continued to see increasing demand for aging analysis, not only in the traditional automotive space, but also in other areas of technology design, such as mobile communication and IoT application... » read more

Design For Reliability


Circuit aging is emerging as a mandatory design concern across a swath of end markets, particularly in markets where advanced-node chips are expected to last for more than a few years. Some chipmakers view this as a competitive opportunity, but others are unsure we fully understand how those devices will age. Aging is the latest in a long list of issues being pushed further left in the desig... » read more

Dealing With Device Aging At Advanced Nodes


Premature aging of circuits is becoming troublesome at advanced nodes, where it increasingly is complicated by new market demands, more stress from heat, and tighter tolerances due to increased density and thinner dielectrics. In the past, aging and stress largely were separate challenges. Those lines are starting to blur for a number of reasons. Among them: In automotive, advanced-node... » read more

Improving Reliability For GaN And SiC


Suppliers of gallium nitride (GaN) and silicon carbide (SiC) power devices are rolling out the next wave of products with some new and impressive specs. But before these devices are incorporated in systems, they must prove to be reliable. As with previous products, suppliers are quick to point out that the new devices are reliable, although there are some issues that can occasionally surface... » read more

What’s Holding Back Aging Simulation?


Aging simulation supplies information about the long-term behavior before an IC enters into production, providing an important early evaluation of the reliability required by the application and specification. Re-designs due to reliability issues, and over-design with excessive safety margins, are avoided in this way. In addition, the long-term stability can be demonstrated to the customer. ... » read more

Toward Consistent Circuit-Level Aging Simulations In Different EDA Environments


Aging simulations on circuit level allow integrated circuit (IC) designers to verify their circuits with respect to lifetime reliability requirements by considering the degradation of field effect transistors (FETs). To obtain significant analysis results with a reasonable effort, two prerequisites have to be fulfilled. First, reasonable models for FET degradation effects have to be set up. Sec... » read more

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