tag: hybrid bonding

A Novel Photosensitive Permanent Bonding Material Designed For Polymer/Metal Hybrid Bonding Applications
By Brewer Science - 18 Aug, 2022 - Comments: 0

Wafer-level hybrid bonding techniques, which provide simultaneous bonding between metal-metal and dielectric-dielectric layers, have attracted more attention in recent years for fabricating 3D integrated circuits with high bandwidth and high interconnect density. However, there are some issues for conventional hybrid bonding using silicon oxide as the dielectric, such as the high stress and low... » read more

Hybrid Bonding Moves Into The Fast Lane
By Laura Peters - 21 Jul, 2022 - Comments: 1

The industry’s unquenchable thirst for I/O density and faster connections between chips, particularly logic and cache memory, is transforming system designs to include 3D architectures, and hybrid bonding has become an essential component in that equation. Hybrid bonding involves die-to-wafer or wafer-to-wafer connection of copper pads that carry power and signals and the surrounding diele... » read more

Technical Paper Round-up: June 14
By Linda Christensen - 14 Jun, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=33 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit f... » read more

Cu/SiO₂ Hybrid Bond Interconnects
By Technical Paper Link - 10 Jun, 2022 - Comments: 0

Technical paper titled "Microstructure Development of Cu/SiO₂ Hybrid Bond Interconnects After Reliability Tests" from researchers at TU Dresden and others. Abstract: "The focus of this study is a detailed characterization of hybrid Cu/SiO 2 wafer-to-wafer bonding interconnects after reliability testing. Hybrid bonding (or direct bond interconnect) is a technology of choice for fine pitch... » read more

Center Stage: The Time For Hybrid Bonding Has Arrived
By Woo Young Han - 07 Jun, 2022 - Comments: 0

When the subject of hybrid bonding is brought up in the industry, the focus is often on how this technique is used to manufacture CMOS image sensors (CIS), an essential device for today’s digital cameras, particularly those found in smartphones. As such, CIS is a common touchpoint given the ubiquity of mobile phones, whether you hold a product from Apple, Samsung, or Huawei in your hands. ... » read more

HBM, Nanosheet FETs Drive X-ray Fab Use
By Laura Peters - 08 Mar, 2022 - Comments: 0

Paul Ryan, vice president and general manager of Bruker’s X-ray Business, sat down with Semiconductor Engineering to discuss the movement of x-ray metrology into manufacturing to better control nanosheet film stacks and solder bump quality. SE: Where are you seeing the greatest growth right now, and what are the critical drivers for your technology from the application side? Ryan: One b... » read more

Data Center Architectures In Flux
By Ann Mutschler - 24 Feb, 2022 - Comments: 0

Data center architectures are becoming increasingly customized and heterogeneous, shifting from processors made by a single vendor to a mix of processors and accelerators made by multiple vendors — including system companies' own design teams. Hyperscaler data centers have been migrating toward increasingly heterogeneous architectures for the past half decade or so, spurred by the rising c... » read more

Next-Gen 3D Chip/Packaging Race Begins
By Mark LaPedus - 31 Jan, 2022 - Comments: 5

The first wave of chips is hitting the market using a technology called hybrid bonding, setting the stage for a new and competitive era of 3D-based chip products and advanced packages. AMD is the first vendor to unveil chips using copper hybrid bonding, an advanced die-stacking technology that enables next-generation 3D-like devices and packages. Hybrid bonding stacks and connects chips usin... » read more

A New Dimension Of Complexity For IC Design
By Ann Mutschler - 27 Jan, 2022 - Comments: 0

Full 3D designs involving logic-on-logic are still in the tire-kicking stage, but gaps in the tooling already are showing up. This is especially evident with static timing analysis (STA), which is used to validate a design’s timing performance by checking all possible paths for timing violations. STA issues began popping up particularly with the introduction of hybrid bonding, a bumpless p... » read more

Future Challenges For Advanced Packaging
By Mark LaPedus - 20 Jan, 2022 - Comments: 1

Michael Kelly, vice president of advanced packaging development and integration at Amkor, sat down with Semiconductor Engineering to talk about advanced packaging and the challenges with the technology. What follows are excerpts of that discussion. SE: We’re in the midst of a huge semiconductor demand cycle. What’s driving that? Kelly: If you take a step back, our industry has always ... » read more

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