All-In-One Analog AI Accelerator With CMO/HfOx ReRAM Integrated Into The BEOL (IBM Research-Europe)


A new technical paper titled "All-in-One Analog AI Hardware: On-Chip Training and Inference with Conductive-Metal-Oxide/HfOx ReRAM Devices" was published by researchers at IBM Research-Europe. Abstract "Analog in-memory computing is an emerging paradigm designed to efficiently accelerate deep neural network workloads. Recent advancements have focused on either inference or training accelera... » read more

Chip Industry Technical Paper Roundup: June 17


New technical papers recently added to Semiconductor Engineering’s library: [table id=440 /] Find more semiconductor research papers here.   » read more

Chip Industry Technical Paper Roundup: Apr. 1


New technical papers recently added to Semiconductor Engineering’s library: [table id=416 /] Find more semiconductor research papers here. » read more

HW Implementation Of An ONN Coupled By A ReRAM Crossbar Array (IBM, TU Eindhoven)


A new technical paper titled "Hardware Implementation of Ring Oscillator Networks Coupled by BEOL Integrated ReRAM for Associative Memory Tasks" was published by researchers at IBM Research Europe and Eindhoven University of Technology. Abstract "We demonstrate the first hardware implementation of an oscillatory neural network (ONN) utilizing resistive memory (ReRAM) for coupling elements. ... » read more

Chip Industry Week In Review


Infineon rolled out the world's first 300mm gallium nitride (GaN) wafer, opening the door for high-volume manufacturing of GaN-based power semiconductors. A 300mm wafer contains 2.3 times as many chips per wafer as a 200mm wafer. Fig.1: Infineon's 300mm GaN wafer. Source: Infineon The Semiconductor Industry Association released its 2024 State of the U.S. Semiconductor Industry report th... » read more

Chip Industry Technical Paper Roundup: Sept. 3


New technical papers recently added to Semiconductor Engineering’s library: [table id=256 /] More ReadingTechnical Paper Library home » read more

Characterizing Three Supercomputers: Multi-GPU Interconnect Performance


A new technical paper titled "Exploring GPU-to-GPU Communication: Insights into Supercomputer Interconnects" was published by researchers at Sapienza University of Rome, University of Trento, Vrije Universiteit Amsterdam, ETH Zurich, CINECA, University of Antwerp, IBM Research Europe, HPE Cray, and NVIDIA. Abstract "Multi-GPU nodes are increasingly common in the rapidly evolving landscape... » read more

Chip Industry Technical Paper Roundup: Mar. 5


New technical papers added to Semiconductor Engineering’s library this week. [table id=201 /] » read more

A Precision-Optimized Fixed-Point Near-Memory Digital Processing Unit for Analog IMC (IBM and ETH Zurich)


A technical paper titled “A Precision-Optimized Fixed-Point Near-Memory Digital Processing Unit for Analog In-Memory Computing” was published by researchers at IBM Research Europe and IIS-ETH Zurich. Abstract: "Analog In-Memory Computing (AIMC) is an emerging technology for fast and energy-efficient Deep Learning (DL) inference. However, a certain amount of digital post-processing is requ... » read more

Chip Industry’s Technical Paper Roundup: August 9


New technical papers recently added to Semiconductor Engineering’s library: [table id=124 /] More Reading Technical Paper Library home » read more

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