New Architectures Redefining The Data Center

By Ed Sperling - 26 Sep, 2013 - Comments: 0

By Ed Sperling The cost of powering and cooling data centers, coupled with a better understanding of how enterprise-level applications can utilize hardware more effectively, are spawning a new wave of changes inside of data centers. Data centers are always evolving, but in this sector that evolution is deliberate and sometimes painstakingly slow. In fact, each major shift tends to last a de... » read more

MRAM Begins To Attract Attention

By Mark LaPedus - 19 Sep, 2013 - Comments: 0

By Mark LaPedus In the 1980s, there were two separate innovations that changed the landscape in a pair of related fields—nonvolatile memory and storage. In one effort, Toshiba invented the flash memory, thereby leading to NAND and NOR devices. On another front, physicists discovered the giant magnetoresistance (GMR) effect, a technology that forms the basis of hard disk drives, magnetores... » read more

HotChips: Power8

By Barry Pangrle - 12 Sep, 2013 - Comments: 2

It’s another year, another HotChips Conference and another update on IBM’s POWER processor. IBM continues to impress with its big iron processor, and this year it’s the new POWER8. IBM announced more details of its new POWER8 processor at HotChips and IBM now joins Intel at 22nm, but with the twist that IBM’s process is based on SOI technology. The POWER8 quadruples the thread count ... » read more

Under One Roof

By Ed Sperling - 12 Sep, 2013 - Comments: 0

By Ed Sperling Microsoft’s decision to buy Nokia’s phone business, Apple’s move to build its own chips to more effectively run its software, and Google’s effort to develop its own hardware for next-generation platforms such as Google Glass mark an interesting reversal in the electronics industry. Disaggregation was the answer to slow-moving giants such as big-iron companies. Startin... » read more

Experts At The Table: Who Pays For Low Power?

By Ed Sperling - 26 Jul, 2013 - Comments: 1

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss the cost of low power with Fadi Gebara, research staff member for IBM’s Austin Research Lab; David Pan, associate professor in the department of electrical and computer engineering at the University of Texas; Aveek Sarkar, vice president of product engineering and support at Apache Design; and Tim Whitfield, director ... » read more

Blog Review: July 24

By Ed Sperling - 24 Jul, 2013 - Comments: 0

By Ed Sperling Mentor’s Harry Foster unleashes part six of the Wilson Research Group functional verification study, this segment digging deeper into the time spent in verification. The numbers have surpassed time spent on the design side, which either means the front-end tools are getting better or the verification problem is becoming more difficult. Cadence’s Brian Fuller interviews I... » read more

Experts At The Table: Who Pays For Low Power?

By Ed Sperling - 19 Jul, 2013 - Comments: 0

GloFo Says 28nm FD-SOI Die Cost Much Less Than 28nm Bulk HPP

By Various Writers - 17 Jul, 2013 - Comments: 0

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News ~ ~ According to Shigeru Shimauchi, Country Manager, GlobalFoundries Japan, for the same level of performance, the die cost for 28nm FD-SOI will be substantially less than for 28nm bulk HPP (“high performance-plus”). Specifically, to get a 30% increase in performance over 28nm bulk LPS PolySiON, HPP increases die ... » read more

Experts At The Table: Who Pays For Low Power?

By Ed Sperling - 11 Jul, 2013 - Comments: 0

The Rise Of Semiconductor IP Subsystems

By Various Writers - 11 Jul, 2013 - Comments: 0

The semiconductor IP (SIP) market arose when SIP vendors created IP functions that mirrored those found in the discrete semiconductor market and made those functions available to SoC designers in the form of hard or soft SIP blocks. As the SoC and SIP markets evolved, it was a natural evolution that many discrete SIP functions be converged into larger blocks that mimic system-level functions (i... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

tag: IBM

New Architectures Redefining The Data Center

MRAM Begins To Attract Attention

HotChips: Power8

Under One Roof

Experts At The Table: Who Pays For Low Power?

Blog Review: July 24

Experts At The Table: Who Pays For Low Power?

GloFo Says 28nm FD-SOI Die Cost Much Less Than 28nm Bulk HPP

Experts At The Table: Who Pays For Low Power?

The Rise Of Semiconductor IP Subsystems