Interconnect Challenges Grow

New breakthroughs being sought for backend-of-line as performance degrades and RC delay increases.

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Qualcomm outlined the technology challenges facing mobile chip suppliers at a recent event. In no particular order, the challenges include the usual suspects—area scaling, power reduction, performance and cost.

Another concern for Qualcomm is an often-overlooked part of the equation—the backend-of-the-line (BEOL). In chip production, the BEOL is where the interconnects are formed within a device. Interconnects, those tiny wiring schemes in devices, are becoming more compact at each node. This, in turn, is causing a degradation in performance and an increase in the dreaded resistance-capacitance (RC) delay in chips.

RC delay has been the topic of concern for years, but the problems won’t go away. In fact, they’re getting worse at the 20nm node and beyond. In just one example of the complexities of the interconnect, the total length of the wires in a device has roughly doubled, from about 2,000 kilometers per square centimeter in 2009 to about 4,000 today, according to Imec. By 2024, that figure could reach 14,000. The measurement only includes wires in the first five metal layers.

To help solve the RC problem, chipmakers are moving toward new materials, such as cobalt (Co) and ruthenium (Ru) in the interconnect. The move also may require new fab tool technologies. But it’s still unclear if the new solutions can halt a troubling trend. “If you look at the projections about what the metal resistance would look like, you can see an exponential increase starting at the 10nm node,” said Geoffrey Yeap, vice president of technology at Qualcomm. “It will be very bad at the 7nm node.”

In total, the BEOL-gate delay gap is projected to increase by about 1,000 times between the 90nm and 10nm nodes, Yeap said. This metric involves the widening delta between two separate curves—the transistor delay and the RC interconnect delay—at a given node.

And for the first time, the BEOL is projected to exceed 50% of the total process cost for a mobile chip starting at 10nm, he said. That figure includes both lithography and materials processing costs. “BEOL RC performance as well as area/cost scaling are issues that require materials innovation urgently and cost-effectively,” he added.

Daniel Edelstein, an IBM fellow and manager of BEOL technology strategy at IBM, took issue with some of Qualcomm’s figures, but he agreed that the problems will escalate at 10nm, if not sooner. “Sometimes, people quote worse than the worst case metrics in terms of what the RC delay would be for the narrowest/thinnest wire used to signal across the entire chip,” Edelstein said. “But yes, there are big concerns. Scaling causes line resistance, or resistance per unit length, to blow up, simply by quadratic scaling of the wire cross-sectional area. In addition, even scaled-length wire resistance is still increasing much faster than it used to.”

Adding to the problems are that the BEOL will require complex and expensive multiple pattering schemes starting at 20nm and beyond. “The lack of EUV lithography requires pitch splitting, which greatly drives up the cost as more wiring levels will be required,” he added.

Backend blues
For years, there were two basic types of BEOL interconnect wires, intermediate and global. In a chip, the intermediate wires provide the lower-level connections between the metal one layer and the synchronous modules.

As before, the problems associated with RC delay reside with the global wires, which connect the intermediate layers with the asynchronous modules in a device. “The global wires have the longest lines,” said Zsolt Tokei, a program director at Imec. “They represent most of the problems.”

Adding to the issues is that chipmakers have inserted yet another wiring hierarchy starting at 20nm. The scheme, dubbed the middle-of-the-line (MOL), involves the local interconnects in a design. “This improves area scaling,” Tokei said. “There are obvious drawbacks. One is process cost complexity.”

Basically, the formation of the traditional BEOL requires several process steps, such as lithography, metallization and others. The separate MOL adds yet another new and expensive process flow to the mix, which also includes lithography and metallization. “There is a drastic cost increase for 20nm,” Qualcomm’s Yeap said. “That’s because you have a new module called the middle-of-the-line local interconnect. That darn thing in 20nm costs five masks. If you project that to 10nm, that number can easily double.”

In fact, at 10nm, chipmakers could end up migrating to a different and costly interconnect scheme, which makes use of self-aligned local interconnects to a sidewall spacer, according to Imec. Then, by 7nm, the industry may deploy self-aligned contacts, according to the R&D organization.

Looking for breakthroughs
Still, the global wires remain the biggest challenge within the BEOL. In this area, the real action is taking place in the copper dual damascene process. This process involves three main parts—metallization; low-k dielectrics; and the capping layer. In the metallization step, a structure undergoes a diffusion barrier etch step. Then, a via dielectric is deposited. An etch step then forms a gap, where the lines and vias are formed.

Then, a thin barrier layer of tantalum (Ta) and tantalum nitride (TaN) materials is deposited using physical vapor deposition (PVD). Ta is used to form the liner and TaN is for the barrier in a structure. The barrier layer is coated over by a copper (Cu) seed barrier via PVD. And finally, the structure is electroplated with copper and ground flat using chemical mechanical polishing (CMP).

This process works for today’s chips, but wire resistance is increasing at an alarming rate as the interconnect is scaled to 20nm and beyond. This is due to a decrease of copper in the lines and electron scattering. Scaling also limits thicker seed copper deposition with today’s PVD tools.

In fact, PVD was supposed to run out of gas years ago. PVD is a deposition method that involves high-temperature vacuum evaporation and sputtering. The successor to PVD was supposedly atomic layer deposition (ALD), which deposits conformal thin-films one atom at a time.

As it turns out, PVD continues to extend, thereby pushing out ALD. “People wondered if PVD would extend to the 130nm node,” said Kevin Moraes, director of global product management within the Metal Deposition Product Business Group at Applied Materials. “PVD will extend to 10nm. For 10nm, PVD is the primary approach.”

On the materials front, the industry will likely stick with TaN for the barrier at 14nm and 10nm. “From the barrier standpoint, the industry is still trying tantalum nitride. That’s really based on an improvement of the deposition capabilities,” Moraes said.

At 7nm, however, the industry is exploring other technologies for the barrier. “There has been a lot of work on manganese-silicate barriers. There are a lot of challenges, which have yet to be resolved,” he said.

However, for the liner at 14nm and 10nm, chipmakers may make the transition from Ta to either Co or Ru, according to Imec’s roadmap. If so, the industry could switch from PVD to chemical vapor deposition (CVD). “Instead of tantalum, you can use either cobalt or ruthenium to act as a liner. Both of them have good characteristics with copper,’’ Moraes said.

There are some tradeoffs. “Ruthenium has good wetting capabilities. Copper moves on it easily. However, ruthenium is very challenging from a CMP standpoint. Cobalt doesn’t wet as easily. Cobalt has a different behavior with copper,” he added.

At 10nm and 7nm, the leading candidate is a CVD-enabled Ru liner. The challenges with Ru are defects and performance degradation. At the recent International Electron Devices Meeting (IEDM) in Washington, D.C., Samsung showed an Ru liner technology without TDDB performance degradation.

In the lab, Samsung devised a copper dual damascene structure. Using CVD, Ru was applied as a liner. The structure was tested with two types of ultra low-k films at 2.5, a conventional and a robust version. The robust low-k film was optimized with a silicon precursor and a bridged carbon. Both low-k materials were processed using PECVD and thermo-UV cures. This, in turn, formed pores within the films and Si-O network bonds.

The robust low-k film limited water absorption during CMP, thereby resulting in a longer TDDB, according to Samsung. All told, the CVD-enabled Ru liner had 20% less resistance, compared to conventional PVD-based Ta, according to Samsung.

Still, there is plenty of work to do in the arena. “We and others have reported on alternate barriers for improved copper gap fill,” said IBM’s Edelstein. “Both Co and Ru have performance penalties, and are not adequate barriers on their own. Mn self-formed barriers also have issues.”

Meanwhile, Samsung’s work also underscores the need to bolster another critical piece of the puzzle, low-k dielectrics. This technology is moving at a snail’s pace amid a slew of challenges. The films suffer from poor mechanical properties and are prone to potential damage during CMP.

“These films are basically porous,” said Terrance Lee, a product manager at Applied Materials. “So, the whole idea there is to drive out the porosity in a uniform manner. What we want to do is not only have a reliable film, but also have a very good on-wafer performance. And after the formation of the film, there is still the entire integration challenge.”

For today’s chips, the “k” value for low-k is around 2.5. At 14nm, the industry is looking to insert low-k films with a “k” value at 2.2. The ultimate value is 1.0, which is an air-gap technology. Air gaps, in fact, could solve one large piece of the RC puzzle. “Air gap is always on the roadmap, but it continues to get pushed out. It’s not 10nm for sure. It’s less than 10nm. It boils down to what is the real benefit and the trade-off on reliability,” Lee said.

Needless to say, the interconnect is expected to be a challenge at 7nm and beyond. On Imec’s roadmap, there are few, if any, solutions beyond 7nm. In the distant future, the industry has talked about using carbon nanotubes and graphene as interconnects. Those technologies are still R&D curiosities, leaving many to believe that the industry will require new breakthroughs in the BEOL.