Memory Gets Smarter

By Ed Sperling - 27 Jun, 2013 - Comments: 0

By Ed Sperling Look inside any complex SoC these days and the wiring congestion around memory is almost astounding. While the number of features on a chip is increasing, they are all built around the same memory modules. Logic needs memory, and in a densely packed semiconductor, the wires that connect the myriad logic blocks are literally all over the memory. This is made worse by the fact ... » read more

Inside A 450mm Metrology Consortium

By Mark LaPedus - 20 Jun, 2013 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss 450mm metrology challenges with Menachem Shoval, a former manufacturing executive at Intel and chairman of the Metro450 consortium. The Israeli-based consortium is developing metrology technology for the next-generation, 450mm wafer size. The group consists of Intel, Applied Materials, Jordan Valley, Nanomotion, Nov... » read more

Consortium Mania Sweeps 450mm Landscape

By Mark LaPedus - 20 Jun, 2013 - Comments: 0

By Mark LaPedus In the mid-1990s, the semiconductor industry embarked on a costly and problematic migration from 200mm to 300mm wafer fabs. At the time, the 300mm development efforts were in the hands of two groups—Sematech and a Japanese-led entity. The equipment industry was on the outside looking in. And as a result, the migration from 200mm to 300mm fabs was out of sync and a nightma... » read more

3D-IC Testing With The Mentor Graphics Tessent Platform

By Various Writers - 20 Jun, 2013 - Comments: 0

Three-dimensional stacked integrated circuits (3D-ICs) are composed of multiple stacked die, and are viewed as critical in helping the semiconductor industry keep pace with Moore's Law. Current integration and interconnect methods include wirebond and flip-chip and have been in production for some time. 3D chips connected via interposers are in production at Xilinx, Samsung, IBM, and Sematec... » read more

VLSI Kyoto – The SOI Papers

By Various Writers - 19 Jun, 2013 - Comments: 0

By Adele Hars There were some breakthrough FD-SOI and other excellent SOI-based papers that came out of the 2013 Symposia on VLSI Technology and Circuits in Kyoto (June 10-14, 2013). By way of explanation, VSLI comprises two symposia: one on Technology; one on Circuits. However, papers that are relevant to both were presented in “Jumbo Joint Focus” sessions. The papers should all b... » read more

Scaling The Lowly SRAM

By Mark LaPedus - 05 Jun, 2013 - Comments: 0

By Mark LaPedus Chipmakers face a multitude of challenges at the 20nm logic node and beyond, including the task of cramming more functions on the same chip without compromising on power and performance. There is one major challenge that is often overlooked in the equation—scaling the lowly static RAM (SRAM). In one key application, SRAM is the component used to make on-chip cache memories... » read more

The Bumpy Road To 450mm

By Mark LaPedus - 16 May, 2013 - Comments: 0

By Mark LaPedus After its formation nearly 20 months ago, a 450mm consortium has reached its latest milestone by recently completing a cleanroom and installing the first 450mm demonstration tools in the facility. The so-called Global 450 Consortium (G450C) also has set a goal to bring 450mm fabs into high-volume manufacturing at the 10nm or 7nm nodes by 2018. That gives the industry a littl... » read more

New Foundry Gold Rush: RF SOI

By Mark LaPedus - 16 May, 2013 - Comments: 0

By Mark LaPedus About every five years or so, a new and hot market emerges in the specialty foundry business that resembles a frenetic gold rush. The last big gold rush occurred around 2008, when more than a dozen foundries jumped into the bipolar-CMOS-DMOS (BCD) market to capitalize on the booming power-management sector. Now, the next gold rush is centering on an emerging technology—th... » read more

Bigger Wafers, Bigger Risk

By Ed Sperling - 16 May, 2013 - Comments: 0

At 22/20/16/14nm the semiconductor industry is experiencing a rather new twist on Moore’s Law. Smaller, as in smaller feature sizes, is no longer assumed to be cheaper—or at least not for everyone. In fact, the cost per transistor for the first time in more than half a century could rise in some cases. Whether this outlook improves as the semiconductor industry gains more experience wit... » read more

FinFET Isolation: Bulk vs. SOI

By Various Writers - 15 May, 2013 - Comments: 1

Terry Hook of IBM recently contributed an article to ASN about FinFET isolation issues on bulk vs. SOI. It generated immense interest, and created lots of discussion on various LinkedIn groups. In case you missed it, here it is again. (This article is based on an in-depth presentation Terry gave at the SOI Consortium's Fully-Depleted Tech Workshop, held during VLSI-TSA in Taiwan, April 2... » read more

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Knowledge Centers
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Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

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