tag: IBM

Scaling The Lowly SRAM
By Mark LaPedus - 05 Jun, 2013 - Comments: 0

By Mark LaPedus Chipmakers face a multitude of challenges at the 20nm logic node and beyond, including the task of cramming more functions on the same chip without compromising on power and performance. There is one major challenge that is often overlooked in the equation—scaling the lowly static RAM (SRAM). In one key application, SRAM is the component used to make on-chip cache memories... » read more

The Bumpy Road To 450mm
By Mark LaPedus - 16 May, 2013 - Comments: 0

By Mark LaPedus After its formation nearly 20 months ago, a 450mm consortium has reached its latest milestone by recently completing a cleanroom and installing the first 450mm demonstration tools in the facility. The so-called Global 450 Consortium (G450C) also has set a goal to bring 450mm fabs into high-volume manufacturing at the 10nm or 7nm nodes by 2018. That gives the industry a littl... » read more

New Foundry Gold Rush: RF SOI
By Mark LaPedus - 16 May, 2013 - Comments: 0

By Mark LaPedus About every five years or so, a new and hot market emerges in the specialty foundry business that resembles a frenetic gold rush. The last big gold rush occurred around 2008, when more than a dozen foundries jumped into the bipolar-CMOS-DMOS (BCD) market to capitalize on the booming power-management sector. Now, the next gold rush is centering on an emerging technology—th... » read more

Bigger Wafers, Bigger Risk
By Ed Sperling - 16 May, 2013 - Comments: 0

At 22/20/16/14nm the semiconductor industry is experiencing a rather new twist on Moore’s Law. Smaller, as in smaller feature sizes, is no longer assumed to be cheaper—or at least not for everyone. In fact, the cost per transistor for the first time in more than half a century could rise in some cases. Whether this outlook improves as the semiconductor industry gains more experience wit... » read more

FinFET Isolation: Bulk vs. SOI
By Various Writers - 15 May, 2013 - Comments: 1

Terry Hook of IBM recently contributed an article to ASN about FinFET isolation issues on bulk vs. SOI.  It generated immense interest, and created lots of discussion on various LinkedIn groups.  In case you missed it, here it is again. (This article is based on an in-depth presentation Terry gave at the SOI Consortium's Fully-Depleted Tech Workshop, held during VLSI-TSA in Taiwan, April 2... » read more

The Power Problem
By Ed Sperling - 09 May, 2013 - Comments: 0

For the past few years, EDA companies have been warning chipmakers that power will become the biggest issue they face at future nodes. They were right. While it may not be the only big problem—after all, the number of issues at each new tick of Moore’s Law is growing—power is certainly one of the most challenging and by far the most pervasive. In fact, the warnings about just how perni... » read more

Design-For-DSA Industry Begins To Assemble
By Mark LaPedus - 18 Apr, 2013 - Comments: 0

By Mark LaPedus The industry is aggressively pursuing directed self-assembly (DSA) as an alternative patterning technology for future chip designs. DSA, which enables fine pitches through the use of block copolymers, is in the R&D pilot line stage today. The fab tools, process flows and materials are basically ready, but there are still several challenges to bring the technology from th... » read more

Foundry Models In Transition
By Jeff Chappell - 18 Apr, 2013 - Comments: 0

By Jeff Chappell There may have been a time when AMD founder Jerry Sanders famous quote: "real men (i.e., real companies) have their own fabs” rang true, but in today's business climate it seems quaint at best. Fabless or fab-lite business models are more popular than ever today, while some IDMs have turned back the clock, so to speak, looking to improve capacity utilization and revenues ... » read more

Supply Chain Catch-Up
By Ed Sperling - 18 Apr, 2013 - Comments: 0

There always will be a few big companies marching to the latest process node available to them. The problem these days isn’t their commitment to pushing forward. It’s the baggage train following them. It’s getting longer, more diverse, and in some cases, it’s falling out of sync. The foundries are out in front with 14nm finFETs, and they’re already working on 10nm transistors—pos... » read more

Uncertainty Ahead
By Ed Sperling - 11 Apr, 2013 - Comments: 0

If finFETs work as planned, it’s likely they will show up in every complex SoC for decades to come. Adding another dimension to transistors has enormous potential at advanced nodes, and maybe even at older nodes. 3D transistors also could be part of stacked die, and they can be combined with fully depleted SOI—two other options for reducing power. Moreover, it’s likely that whatever G... » read more

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