Manufacturing Bits: Oct. 1

Nanoimprint foundry; all-around process; 3D sans TSVs.


Nanoimprint Foundry
Singapore’s A*STAR’s Institute of Materials Research and Engineering (IMRE) and its partners have launched a new R&D foundry using nanoimprint lithography.

The so-called Nanoimprint Foundry is a collaboration between several entities, such as IMRE, Toshiba Machines, EV Group, NTT, NIL Technology, Kyodo International, Micro Resist Technology, Nanoveu and Solves Innovative Technology.

The goal of the operation is to enable companies to develop and produce prototype products for commercial applications. It is also designed to speed up the development of nanoimprint lithography. Possible applications of nanoimprint include flexible substrates, dry adhesives, packaging, contact lenses, biomedical cell scaffolds, anti-frost surfaces and anti-bacteria materials.

The nanoimprint tools within the foundry are based on roll-to-roll, batch and wafer manufacturing technologies. Roll-to-roll technology, for example, enables the creation of patterned surfaces on flexible substrates. It is targeted for high throughput and room temperature processing at feature sizes of 50nm and below.

Karen Chong, IMRE scientist who is heading the foundry, said the operation is a one-stop shop for companies seeking to develop products based on nanoimprint. “We can help companies develop up to 20,000 samples for proof-of-concept and pilot production allowing manufacturers to shorten the product cycle but minus the heavy capital R&D investment,” Chong said A*STAR’s Web site.

All-Around Fab Process
Today’s finFET transistors are expected to scale to 10nm. Then, the industry is expected to develop high-mobility finFETs, which will incorporate various III-V materials in the channels. The question is what’s after high-mobility finFETs?

It’s still unclear, but experts believe the ultimate device is the gate-all-around (GAA) finFET. GAA-based devices claim to have the best electrostatic characteristics.
At the upcoming IEEE International Electron Devices Meeting (IEDM), IBM will describe a new and improved fabrication process that could enable GAA-based devices at sizes compatible with the scaling needs of 10nm technology. IEDM will take place in Washington, D.C. from Dec. 9-11, 2013.

The process includes the steps to make silicon nanowires (SiNW), which serve as the channels for GAA-based devices. In the original process, the nanowires are retained during the spacer formation using an undoped epitaxial process.

In the new process, the nanowires are removed during the spacer formation using an in-situ doped epitaxial process. In the lab, IBM has built a range of GAA SiNW MOSFETs, some of which feature a 30nm pitch for the nanowires and a 60nm gate pitch. Devices with a 90nm gate pitch demonstrated the highest performance ever reported for a SiNW device at a gate pitch below 100nm. The device had a peak/saturation current of 400/976µA/µm, respectively, at 1 V, according to IBM.

The work focused on NFETs, but the process can be used to produce PFETs as well, opening the door to a potential ultra-dense, high-performance CMOS technology.

3D Sans TSVs
An alternative to traditional logic scaling is 2.5D/3D stacked die. Usually, the chips are staked and connected using through-silicon vias (TSVs). But there are numerous challenges with TSV-based stacked die, such as parasitic capacitance, thermal mismatch issues and others.

At the upcoming IEDM, Taiwan’s National Nano Device Laboratories will describe the development of a 3D chip—without using TSVs. Researchers have fabricated a monolithic sub-50nm 3D chip, which integrates logic, nonvolatile memory and SRAM.

Researchers have built the device from ultrathin-body MOSFETs isolated by 300nm-thick interlayer dielectric layers. They also deposited amorphous silicon and crystallized it with laser pulses. They then used a low-temperature chemical mechanical planarization (CMP) technique to thin and planarize the silicon, enabling the fabrication of 3D devices.

The monolithic 3D architecture includes 3ps logic circuits, 1-T 500ns nonvolatile memories and 6T SRAMs with low noise and small footprints, according to National Nano Device Laboratories.

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