Experts At The Table: Evolving Standards


System-Level Design sat down with Keith Barkley, senior engineer in IBM’s systems and technology group; Steven Schulz, president and CEO of Silicon Integration Initiative (Si2); Yatin Trivedi, director of standards and interoperability programs at Synopsys; Ian Mackintosh, chairman of the OCP International Partnership (OCPIP), and Michael Meredith, vice president of technical marketing at For... » read more

Experts At The Table: Evolving Standards


System-Level Design sat down with Keith Barkley, senior engineer in IBM’s systems and technology group; Steven Schulz, president and CEO of Silicon Integration Initiative (Si2); Yatin Trivedi, director of standards and interoperability programs at Synopsys; Ian Mackintosh, chairman of the OCP International Partnership (OCPIP), and Michael Meredith, vice president of technical marketing at For... » read more

More Cores, Different Approaches


By Ed Sperling The general consensus among software developers is that some applications will never be able to take advantage of multiple cores, but that certainly doesn’t mean system designers can’t figure out ways to use more cores. Nor does it mean that all cores are created equal. The picture that is emerging from multiple chipmakers shows the following trends: More cores have lim... » read more

Hot Chips 2009: It’s All About Multicore And Low-Power


By Pallab Chatterjee The game has changed for processors. The goal now is data throughput, not higher gigahertz and more watts. That shift dominated the presentations at the Hot Chips conference this week. In previous years, the theme was higher single-core performance, more power and smaller geometries processes. This year it was all about multi-core and multi-power options as the realities ... » read more

Restrictive Design Rules, Take Two


By Ed Sperling For the past couple of years, restrictive design rules have been looming over advanced process nodes as the best way to get a chip out the door with minimal re-spins, on schedule and for the least amount of money. Even with immersion technology, 193nm wavelengths mean the laser beam is entirely too large to create the masks used to create complex systems on chip at 32nm and bel... » read more

Mythbusters: Moore’s Law, Low Power And The Future Of Chip Design


By Ed Sperling Contrary to popular belief, Moore’s Law is not in serious trouble. Nor will active power in most devices be reduced to the millivolt or microvolt level anytime in the near future. And chip design will not disappear, be relegated to the push of a button or move offshore from one low-cost wage location to the next until ultimately it gets to a place where no one is paid a salary... » read more

Who’s In Control Now?


By Ed Sperling Power is shifting across the design industry in multiple ways and sometimes across multiple continents, driven by complexity and cost pressures and entirely new forms of competition. On one side of the equation, foundries are dictating more of what goes on up front in the design cycle. Design for manufacturing is a prerequisite at 45nm and below, and they’re the ones dictatin... » read more

Where The Jobs Are


The job market for design and verification engineers seems to be exploding. In the past week, listings have been flooding onto jobs boards for LinkedIn semiconductor design groups. The only trouble is engineers may have to move to get the jobs—sometimes halfway around the globe. There have been a bunch of job postings for semiconductor expertise in India, the United Kingdom, as well as pla... » read more

Pain Points At 22nm And Beyond


By Ed Sperling The roadmap for 22nm has a giant pothole in the middle of it. That hole is supposed to be filled by extreme ultraviolet lithography, or EUV. Instead it is being patched up using immersion lithography, which is about to cause some monumental headaches for design teams. The difference is comparable to a surgeon using a chainsaw instead of a scalpel. The cut isn’t nearly as ... » read more

Writing Software For Low-Power Systems


By Ed Sperling Almost any discussion of software in low power systems these days involves some sort of multicore approach. That is particularly true at 90nm and below. At 65nm, unless there is a very distinct purpose for a low-power single-core device, it probably is utilizing at least two cores, and at 45nm the numbers can continue to rise, depending upon how many functions the chip is being... » read more

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