tag: IBM

New Processes Define New Power Plans
By Ed Sperling - 05 Apr, 2012 - Comments: 0

By Pallab Chatterjee FinFETs, stacked die, heterogeneous interposers, TSVs, 450mm wafers, new interconnects and everything with MEMs and sensors is what the last few weeks have brought. A number of major announcements, technology releases, conference updates have identified these technologies as the future of IC design. At ISQED, Robert Geer, chief academic officer at the College of Nanosca... » read more

Consortium Results (Part 3 of 3): 20nm FDSOI Comes Out Way Ahead
By Various Writers - 27 Mar, 2012 - Comments: 0

The results of the most recent SOI Consortium benchmarking study detail the interest of planar FD-SOI as early as the 28nm and 20nm technology nodes, in terms of performance, power and manufacturability. This 3-part blog series looks further at some of the implications. ~~ The SOI Industry Consortium announcement at the end of the year provided silicon proof that FD-SOI handily bea... » read more

Coherency Becomes A Stack Of Issues
By Ed Sperling - 22 Mar, 2012 - Comments: 0

By Ed Sperling As complexity increases and the industry increasingly shifts away from ASICs to SoCs, the concept of coherency is beginning to look more like a stack of issues than a discrete piece of the design. There are at least five levels of coherency that need to be considered already, with more likely to surface as stacked die become mainstream over the next few years. Perhaps even mo... » read more

Why PCs And Servers Aren’t Going Away
By Ed Sperling - 22 Mar, 2012 - Comments: 0

By Pallab Chatterjee With the rise of mobile appliances, smart phones and tablets, there has been a lot of discussion about the place for PCs, servers, embedded processors and networks. A number of companies have claimed they will rule the world of computing and there will no room for others. Reality seems to be somewhat different, however. The mobile end point devices—smart phones, table... » read more

FD-SOI – Consortium Results (Part 2 of 3): Power and Performance
By Various Writers - 21 Mar, 2012 - Comments: 0

The results of the most recent SOI Consortium benchmarking study detail the interest of planar FD-SOI as early as the 28nm and 20nm technology nodes, in terms of performance, power and manufacturability. This 3-part blog series looks further at some of the implications. ~~ Fully depleted transistor architectures such as Planar FD-SOI, FinFETs (which is also a fully-depleted technolog... » read more

FD-SOI Workshop ppts – STM’s 1st 28nm FD-SOI product line
By Various Writers - 12 Mar, 2012 - Comments: 0

The SOI Consortium’s 6th FD-SOI workshop, held just after ISSCC, yielded some exciting news. Most of the presentations are freely available for downloading from the SOI Consortium website. Here are the highlights. STMicroelectronics In a terrific presentation by Giorgio Cesana, Marketing Director at STMicroelectronics, he revealed that the company would be releasing a major product line b... » read more

FD-SOI – Recent Consortium Results (Part 1 of 3): Manufacturing
By Various Writers - 05 Mar, 2012 - Comments: 0

The most recent SOI Consortium benchmarking study regarding 28nm and 20nm FD-SOI results (silicon-calibrated simulations at the 28nm node of complex circuits including ARM cores and DDR3 memory controllers) covered a lot of ground. This post is part 1 of a 3-part blog series that will be highlighting key points with respect to: 1. manufacturing; 2. power & performance; 3. 20nm benchmarking ... » read more

Different Tradeoffs
By Ed Sperling - 23 Feb, 2012 - Comments: 0

By Ed Sperling The push to “smaller, faster and cheaper” hasn’t changed since ICs were first introduced, but the context for those requirements is beginning to shift—with enormous consequences. What was once done on multiple chips continue to migrate to a single chip or package because of cost, but in some cases the decisions about goes where go well beyond an individual device to i... » read more

Different Tradeoffs
By Ed Sperling - 23 Feb, 2012 - Comments: 0

By Ed Sperling The push to “smaller, faster and cheaper” hasn’t changed since ICs were first introduced, but the context for those requirements is beginning to shift—with enormous consequences. What was once done on multiple chips continue to migrate to a single chip or package because of cost, but in some cases the decisions about goes where go well beyond an individual device to i... » read more

Reverse Engineering
By Ed Sperling - 26 Jan, 2012 - Comments: 0

By Ed Sperling Fabs and foundries frequently have been the savior of flawed designs, fixing problems such as power and performance, identifying design issues and often developing solutions to those problems. Over the next couple of process nodes, and in stacked die that will span multiple processes, there will be far fewer saves coming from the back end. Double and triple patterning, stress... » read more

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