FD-SOI – Recent Consortium Results (Part 1 of 3): Manufacturing

At 28nm and beyond, planar FD-SOI lowers manufacturing risk for high-performance, low-power apps


The most recent SOI Consortium benchmarking study regarding 28nm and 20nm FD-SOI results (silicon-calibrated simulations at the 28nm node of complex circuits including ARM cores and DDR3 memory controllers) covered a lot of ground. This post is part 1 of a 3-part blog series that will be highlighting key points with respect to: 1. manufacturing; 2. power & performance; 3. 20nm benchmarking of planar FD-SOI.


Chipmakers constantly have to manage risk.  Generally it is sensible not to try to engage in more than one major change at a time – geometry shrinks already introduce enough headaches.  So planar FD-SOI devices, which use proven, well-understood design and manufacturing techniques should be particularly appealing for both current and upcoming nodes.

Horacio Mendez, executive director of the SOI Industry Consortium noted that FD-SOI  also represents a low risk in terms of manufacturing for upcoming nodes.

“FD-SOI’s ability to accommodate planar architectures presents much lower manufacturing risk than FinFET,” he said. “This makes FD-SOI an easy-to-implement solution for cost-sensitive applications that require performance and low power consumption in standby and active modes, including mobile electronics such as smart phones and tablet computers.”

For many if not most designers, extending the life of existing planar bulk CMOS designs will make good sense.  With a planar FD-SOI solution, these existing designs and related IP can be migrated in a comparatively straightforward way, producing chips that benefit from the intrinsic advantages of fully depleted wafer technology with minimal risk and lower cost.

(There was an excellent piece in ASN from ARM SOI guru Jean-Luc Pelloie on the logistics and ease of porting from bulk to FD-SOI a few months ago – click here to read it.)

The SOI Consortium also points out that FD-SOI is compatible with all power-reduction techniques used by IC designers – and can even boost the efficiency of some. Furthermore, FD-SOI can accommodate some design tweaks (not available with FinFET designs), such as leveraging dynamic back-bias to increase performance or reduce leakage power in some applications.


About the study:

STMicroelectronics, IBM, ARM, GLOBALFOUNDRIES and other leading semiconductor companies participated, each tackling different aspects of the study. The joint research was performed by using an FD-SOI process to fabricate 28nm chips. Test results on these chips were in line with predictions from computer-based models previously developed to benchmark FD-SOI device performance, confirming the models’ reliability – key for both designers and foundries.

Next —  Part 2 of this blog series on the SOI Consortium study looks at FD-SOI from a power & performance perspective.

Leave a Reply

(Note: This name will be displayed publicly)