FD-SOI Workshop ppts – STM’s 1st 28nm FD-SOI product line

The SOI Consortium’s FD-SOI workshop (after ISSCC) yielded exciting news. Here’s highlights.


The SOI Consortium’s 6th FD-SOI workshop, held just after ISSCC, yielded some exciting news. Most of the presentations are freely available for downloading from the SOI Consortium website. Here are the highlights.


In a terrific presentation by Giorgio Cesana, Marketing Director at STMicroelectronics, he revealed that the company would be releasing a major product line based on planar FD-SOI at the 28nm node this year. Prototypes will be ready in June.

The objective, he said, is “…to have a compelling technology offer for the mobile application processor speed race.”

And compelling it is: their 28nm FD-SOI technology performances is 61% higher than comparable bulk technology at 1V. It gets even more interesting at lower Vdd – boasting a 550% improvement at 0.6V.

Slide 32 from ST's presentation, 28 & 20nm FDSOI Technology Platforms, given at the SOI Consortium's 6th FD-SOI Workshop (Feb. 24, 2012).

Check out the presentation – it’s got excellent descriptions, detailed roadmaps (look for products on 20nm FD-SOI in 2014), and clear comparisons. Topics include:

  • 28FDSOI positioning vs. bulk technologies
  • Design methodology and EDA flow
  • From spice models to product: migration methodology from Bulk to FDSOI
  • Biasing techniques on FDSOI
  • FDSOI ST design environment
  • 20FDSOI development track


In FD-SOI Design Portability, Betina Hold, Senior Principal for Silicon R&D at ARM in San Jose emphasized the ease of porting existing designs from bulk to FD-SOI.

FD-SOI, she concluded, is perfect for high-performance, low-power mobile apps.

Here are the main points she made:

Slide 29 from ARM's presentation, FDSOI Design Portability, given at the SOI Consortium's 6th FD-SOI Workshop (Feb. 24, 2012).

(You can also read ARM’s perspective on the ease of porting from bulk to FD-SOI in a recent ASN article by the company’s Director of SOI Technology, Jean-Luc Pelloie.)


There were two presentations from IBM, addressing the two major flavors of fully-depleted architectures on SOI: planar FD-SOI, and FinFETs on SOI.

The presentation entitled Recent Advances in FDSOI given by Bruce Doris, Manager of Device Integration at IBM Research, reviewed various device structures. He presented new data indicating that FD-SOI performance is competitive for high performance and at a much shorter gate lengths (Lg), and will scale well beyond 20nm.

FINFET on SOI presented by Terence Hook, Senior Technical Staff Member at IBM, compared with both clarity and depth the characteristics and manufacturability of FinFETs on SOI and bulk with other SOI and bulk structures.


In a very in-depth presentation, FDSOI strain options FDSOI for 20nm and below, Olivier Faynot, who leads the Innovative Devices Lab at CEA-Leti, demonstrated how most of the existing techniques used on bulk technology are compatible with FDSOI. However, he emphasized that FDSOI devices already meet high performance requirements, especially at the circuit level. A unique feature of FDSOI for future nodes, he noted, is that strained SOI wafers (sSOI – wherein the top layer of silicon is strained at the wafer level) are particularly effective in giving NMOS a boost  (Ion NFET 1.4mA/µm – PFET 1.2 mA/µm @ Ioff 100nA/µm).


Enabling Substrate Technology for a Large Volume FD Standard, presented by Christine Pelissier, Director of Business Operations at SOI wafer manufacturer Soitec, gave a broad view of the both the technological and volume supply requirements for the wafers. Soitec is now manufacturing wafers for FDSOI in which the top silicon is controlled to within +/-5 angstroms.

She looked both at the wafers used in FDSOI as well as the partially depleted (PD) SOI wafers which have been in high-volume production for over a decade. She then went on to explain the key features in wafers for planar FDSOI (which Soitec refers to as FD2D) and in wafers for SOI-based FinFETs (FD3D).

Slide 8 from Soitec's presentation, Enabling Substrate Technology for a Large Volume Fully Depleted Standard, given at the SOI Consortium's 6th FD-SOI Workshop (Feb. 24, 2012).

Other highlights

Two presentations are not available online. Brian Chen of Agilent (Accelicon) presented 20nm ETUTBB-FDSOI Rev3 Models. (Note that 20nm FD-SOI logic evaluation model cards are now available through SOI Consortium in cooperation with Accelicon/Agilent. An NDA is required.)

Professor Borivoje Nikolic from UC Berkeley presented Microprocessor Design in FD-SOI. This showed their design of a Planar FDSOI microprocessor that will be taped out later this year.

In all, this 6th workshop acknowledged the reality of Planar FDSOI technology starting with the 28nm node. There were plenty of relevant questions and discussions, confirming the promise FDSOI holds as a cost-effective and reliable solution.

As Horacio Mendez, Executive Director of the SOI Consortium concluded, this workshop was great. “We’ve been offering these workshops for over two years,” he said. “The community has taken Fully Depleted SOI from a technical advantage in the lab to a technical advantage on mobile products (as presented by ST). The cost, power, performance and manufacturability of FD SOI is a significant driving force.”



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