What Will That Chip Cost?

By Brian Bailey - 30 Oct, 2023 - Comments: 1

In the past, analysts, consultants, and many other experts attempted to estimate the cost of a new chip implemented in the latest process technology. They concluded that by the 3nm node, only a few companies would be able to afford them — and by the time they got into the angstrom range, probably nobody would. Much has changed over the past few process nodes. Increasing numbers of startups... » read more

High-Performance P-Type FET Arrays With Single-Crystal 2D Semiconductors And Fermi-Level-Tuned vdW Contact Electrodes

By Technical Paper Link - 15 Aug, 2023 - Comments: 0

A technical paper titled “Fabrication of p-type 2D single-crystalline transistor arrays with Fermi-level-tuned van der Waals semimetal electrodes” was published by researchers at Ulsan National Institute of Science and Technology (UNIST), University of Pennsylvania, Institute for Basic Science (IBS), Sogang University, and Changwon National University. Abstract: "High-performance p-type t... » read more

10 Questions: Handel Jones

By Ed Sperling - 20 Sep, 2022 - Comments: 0

Handel Jones, CEO of International Business Strategies and author of a new book, "When AI Rules The World," sat down with Semiconductor Engineering to talk about the growth and impact of AI. What follows are excerpts of that conversation. SE: What do you see as the impact of AI on semiconductors? Jones: The fact that you have a 5G smart phone is because of AI. Steve Jobs changed the smart... » read more

Improving PPA With AI

By John Koon - 12 May, 2022 - Comments: 0

AI/ML/DL is starting to show up in EDA tools for a variety of steps in the semiconductor design flow, many of them aimed at improving performance, reducing power, and speeding time to market by catching errors that humans might overlook. It's unlikely that complex SoCs, or heterogeneous integration in advanced packages, ever will be perfect at first silicon. Still, the number of common error... » read more

Week In Review: Manufacturing, Test

By Mark LaPedus - 04 Mar, 2022 - Comments: 0

Packaging ASE, AMD, Arm, Google, Intel, Meta, Microsoft, Qualcomm, Samsung, and TSMC have announced the formation of a consortium that will establish a die-to-die interconnect standard and foster an open chiplet ecosystem. The founding companies also ratified the UCIe specification, an open industry standard developed to establish a standard interconnect at the package level. The UCIe 1.0 s... » read more

Transistors Reach Tipping Point At 3nm

By Mark LaPedus - 23 Feb, 2022 - Comments: 1

The semiconductor industry is making its first major change in a new transistor type in more than a decade, moving toward a next-generation structure called gate-all-around (GAA) FETs. Although GAA transistors have yet to ship, many industry experts are wondering how long this technology will deliver — and what new architecture will take over from there. Barring major delays, today’s GAA... » read more

Improving PPA In Complex Designs With AI

By John Koon - 14 Feb, 2022 - Comments: 0

The goal of chip design always has been to optimize power, performance, and area (PPA), but results can vary greatly even with the best tools and highly experienced engineering teams. Optimizing PPA involves a growing number of tradeoffs that can vary by application, by availability of IP and other components, as well as the familiarity of engineers with different tools and methodologies. Fo... » read more

Week In Review: Manufacturing, Test

By Mark LaPedus - 07 Jan, 2022 - Comments: 0

Fab tools A fire broke out this week within ASML’s factory in Berlin, Germany. The fire was quickly extinguished and no one was injured during this incident. The factory manufactures components for ASML’s lithography systems, including wafer tables and clamps, reticle chucks and mirror blocks. The fire took place on Jan. 3. On Jan. 7, ASML provided an update. "The manufacturing of DUV c... » read more

China Accelerates Foundry, Power Semi Efforts

By Mark LaPedus - 22 Nov, 2021 - Comments: 4

China has unveiled several initiatives to advance its domestic semiconductor industry, including a new and massive fab expansion campaign in the foundry, gallium-nitride (GaN), and silicon carbide (SiC) markets. The nation is making a big push into what it calls “third-generation semiconductors,” which is a misnomer. The term actually refers to two existing and common power semiconductor... » read more

Week In Review: Manufacturing, Test

By Mark LaPedus - 19 Nov, 2021 - Comments: 0

Chipmakers China’s Tsinghua Unigroup is in trouble. The group is the parent company of China’s YMTC, a 3D NAND supplier, and other chip ventures. It is close to moving into bankruptcy proceedings. Now, a consortium led by Alibaba has emerged as the frontrunner to take over Tsinghua Unigroup, according to a report from Bloomberg. That deal would keep the company afloat, the report said. ... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: IBS

What Will That Chip Cost?

High-Performance P-Type FET Arrays With Single-Crystal 2D Semiconductors And Fermi-Level-Tuned vdW Contact Electrodes

10 Questions: Handel Jones

Improving PPA With AI

Week In Review: Manufacturing, Test

Transistors Reach Tipping Point At 3nm

Improving PPA In Complex Designs With AI

Week In Review: Manufacturing, Test

China Accelerates Foundry, Power Semi Efforts

Week In Review: Manufacturing, Test