tag: IEEE 1801

Power Challenges In ML Processors
By Brian Bailey - 12 Mar, 2020 - Comments: 0

The design of artificial intelligence (AI) chips or machine learning (ML) systems requires that designers and architects use every trick in the book and then learn some new ones if they are to be successful. Call it style, call it architecture, there are some designs that are just better than others. When it comes to power, there are plenty of ways that small changes can make large differences.... » read more

Effective Elements List And Transitive Natures Of UPF Commands
By Mentor, a Siemens Business - 15 Jul, 2019 - Comments: 0

Although UPF is very well defined through IEEE 1801 LRM, it is often difficult to comprehend many primitive and inherent features of individual UPF commands-options or relations between different varieties of UPF commands-options. In this paper, we provide a simplistic approach to find inherent links between UPF commands-options through their transitive nature. We also explain how these inheren... » read more

What Happened To UPF?
By Brian Bailey - 16 Apr, 2018 - Comments: 1

Two years ago there was a lot of excitement, both within the industry and the standards communities, about rapid advancements that were being made around low-power design, languages and methodologies. Since then, everything has gone quiet. What happened? At the time, it was reported that the [gettech id="31043" comment="IEEE 1801"] committee was the largest active committee within the IEEE. ... » read more

Power Modeling and Analysis
By Brian Bailey - 20 Sep, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss power modeling and analysis with [getperson id="11489" p_name="Drew Wingard"], chief technology officer at [getentity id="22605" e_name="Sonics"]; [getperson id="11763" comment="Tobias Bjerregaard"], chief executive officer for [getentity id="22908" e_name="Teklatech"]; Vic Kulkarni, vice president and chief strategy officer at [getentity id="22021"... » read more

Power Options And Issues
By Ann Mutschler - 08 Sep, 2016 - Comments: 0

In the quest to get SoC power right as early as possible in the design flow, it still holds true that the biggest impact occurs at the beginning of the project, with diminished results as a design progresses through the flow toward tapeout. [getentity id="22186" e_name="ARM's"] big.LITTLE architecture has gained a lot of traction here, prompting MediaTek to introduce its Tri-Gear big.Medium.... » read more

Bridging the IP Divide
By Brian Bailey - 18 May, 2016 - Comments: 1

IP reuse enabled greater efficiency in the creation of large, complex SoCs, but even after 20 years there are few tools to bridge the divide between the IP provider and the IP user. The problem is that there is an implicit fuzzy contract describing how the IP should be used, what capabilities it provides, and the extent of the verification that has been performed. IP vendors have been trying to... » read more

Is Low Power Coverage Achievable?
By Srikanth Jadcherla - 12 May, 2016 - Comments: 0

Back in 2005, yes, before the invention of the iPhone, I made a slide to educate users on what to cover in Low Power Verification. Using a simple 3 island test case, I illustrated that verification had to be done in 4 states of operation, with 8 transitions and 16 sequences to be verified. This is after pruning the theoretically possible set of 8 states for on/off voltage islands. More than ... » read more

Mixed-Signal Design Powers Ahead
By Ann Mutschler - 10 Mar, 2016 - Comments: 1

Mixed-signal devices are at the heart of many advanced systems today because of the need to interact with the outside world, but designing and verifying these systems is getting harder. There are several reasons for this. First, almost all of these devices now have to be lower power than in the past, and in the analog space it's not as simple as just dialing down part of a block. Second, it ... » read more

Verification Facing Unique Inflection Point
By Brian Bailey - 10 Mar, 2016 - Comments: 0

The Design and Verification Conference and Exhibition (DVCon) attracted more than 1,100 people to San Jose last week, just slightly less than last year. While a lot of focus, and most of the glory, goes to design within semiconductor companies, it is verification where most of the advancements are happening and thus the bigger focus for DVCon. The rate of change in verification and the producti... » read more

Powerful New Standard
By Brian Bailey - 02 Mar, 2016 - Comments: 1

In December 2015, the IEEE released the latest version of the 1801 specification, titled the IEEE standard for design and verification of low-power integrated circuits, but most people know it as UPF or the Unified Power Format. The standard provides a way to specify the power intent associated with a design. With it, a designer can define the various power states of the design and the contexts... » read more

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