Automating Coverage And Analysis Of Low Power Designs

There are some exciting new things in the just released IEEE1801-2015 (aka UPF 3.0), some of which have significant benefits for coverage of low power designs, which is what we’ll be looking at in this blog. One of these is improved semantics for the add power state command, introduced in IEEE1801-2009 (aka UPF 2.0). These clarifications to the add power state command allow you to clearly ... » read more

Powerful New Standard

In December the IEEE released the latest version of the 1801 specification, entitled the IEEE standard for design and verification of low-power integrated circuits. Most people know it as UPF, or the Unified Power Format. That was the name the first version of it held while being developed within Accellera. The standard provides a way to specify the power intent associated with a design, enabli... » read more

One Flow To Rule Them All

The new mantra of shift left within EDA is nothing new and first made an appearance more than a decade ago. At that time there was a very large divide between logic synthesis and place and route. As wire delays became more important, timing closure became increasingly difficult with a logic synthesis flow that did not take that into account. The tools subsequently became tied much closer togeth... » read more

Power Estimation: Early Warning System Or False Alarm?

Semiconductor Engineering sat down with a large panel of experts to discuss the state of power estimation and to find out if the current levels of accuracy are sufficient to being able to make informed decisions. Panelists included: Leah Schuth, director of technical marketing in the physical design group at [getentity id="22186" comment="ARM"]; Vic Kularni, senior vice president and general ma... » read more

Mentor, Cadence Join Forces

Mentor Graphics and Cadence have agreed to create a single binary interface for their respective simulation and emulation platforms, allowing debug tools from one vendor to run on the other's platforms. The two have invited [getentity id="22035" e_name="Synopsys"] to join their initiative, as well. So far, there is no decision. The move proposes a single API for both [getentity id="22032"... » read more

UPF-Driven RTL Power Budgeting For Energy-Efficient Designs

Energy efficiency of devices has become more critical than ever, with shrinking geometries and increased performance requirements of SoCs in applications ranging from mobile, storage, automotive to processors. Power management, therefore, becomes an important part of IP and SoC design methodology. While power management is critical in all design stages, an important aspect of this methodolog... » read more

Extending UPF For Use In System-Level Design

Energy efficiency as a design constraint continues to dominate, and now that we see greater momentum behind a shift left toward system-level design, we are naturally seeing power-aware system-level design as a key area for EDA and IP enablement, especially among mobile and IoT platform providers. In my last article I highlighted the role that IP power models play in the architecture and design ... » read more

An Update On The IEEE 1801-2013 Unified Power Format Standard

It’s been almost six years since the first IEEE 1801 standard was officially published in March of 2009, but the standard can trace its roots back to years before that date. On May 30, 2013 the IEEE released a press announcement for the most recent version of the standard, IEEE 1801-2013 (a.k.a. UPF 2.1). This brought forward a standard for the industry that is finally backed by all of the ma... » read more

Unraveling Power Methodologies

When working on articles, the editors at Semiconductor Engineering sometimes hear things that make them stand back and question what seems to be an industry truth. One such statement happened last month while researching a different article. The statement was: Most designs are not top-down, but in fact bottom-up when it comes to power management. The most used methodology today is that the RTL... » read more

The Week In Review: Design

Tools Cadence unveiled two new tools. The first is a rapid prototyping platform that the company claims will shorten bring-up time by 70%, with 4X improvements in capacity, with IEEE 1801 support for low-power verification through its emulation platform. The second is a single and multi-corner custom/analog extraction tool, which it claims will improve performance by 5X. The tool has been cert... » read more

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