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The Week In Review: Design


Tools Cadence unveiled two new tools. The first is a rapid prototyping platform that the company claims will shorten bring-up time by 70%, with 4X improvements in capacity, with IEEE 1801 support for low-power verification through its emulation platform. The second is a single and multi-corner custom/analog extraction tool, which it claims will improve performance by 5X. The tool has been cert... » read more

S-L Power Modeling Gains Steam


Power analysis, architectural exploration and optimization of an SoC is a hot topic of discussion today. It is well accepted this must be addressed at a higher level of abstraction because not just the hardware must be taken into account with power intent and power management structures. It has to be viewed from a system point of view, as well, where the hardware resides along with the opera... » read more

New Standard!


It’s been a little over four years since the first IEEE 1801 standard was officially published in March 2009, but the standard can trace its roots back to years before that date. On May 30th, the IEEE released a press announcement for the newest version of the standard, IEEE 1801-2013 (a.k.a. UPF 2.1). It takes a considerable amount of effort and attention to detail to produce a solid standar... » read more

What’s Missing In Low-Power Verification


By Ed Sperling Ask two engineers what low-power verification is and you’ll likely get the same checklist that includes confidence in the overall design, good coverage, a long list of corner cases, and other items in a checklist. Ask them how to reach that goal you’ll almost certainly get different answers—or maybe no answers at all. Power has emerged as a ubiquitous concern in design,... » read more

Version Control


By Ed Sperling & Ann Steffora Mutschler One of the biggest impediments to progress in semiconductor design is progress itself—version after version of specifications, formats and increasingly IP. In fact, there are so many different versions, some of which conflict directly with each other, that it may take months or even years before some customers adopt new products. Much has ... » read more

There Can Be Only One


By Cary Chin The tagline of the 1986 fantasy film “Highlander” implies that, at least in some instances, we eventually will arrive at a single, best solution for our problems. In the case of low-power design, the most obvious application of the phrase is in the standardization of low power intent formats, where the Unified Power Format (UPF) and the Common Power Format (CPF) have been lock... » read more

Status Report: Power-Aware Design Flow


By Ann Steffora Mutschler While the term “design flow” can be a moving target, there are some specific requirements for a low-power/power-aware tool flow. Looking at this from a high level, where is the industry today, and where is it headed? There are really two sides to power, which are almost like two sides of the same coin: power consumption and power integrity. And both of those ar... » read more

Power Intent Formats: Isolation


By Luke Lang Last month, I discussed power domain for all three power formats: CPF, UPF 1.0, and IEEE 1801. I mentioned isolation but mainly used it to explain power domain. This month’s blog will address isolation in detail. First, isolation cells are required at off-to-on domain crossings. When a domain is shut off, all of its output nets become undriven. If these floating nets drive direct... » read more

Power Intent Formats: Power Domain


By Luke Lang Starting this month, I will be writing a series of blogs inspired by “Dueling Power Formats”. The article correctly points out that there are currently three power formats: CPF, UPF 1.0, and IEEE 1801. Some designers will find themselves in a position of having to choose a format. Others will need to work with both formats. Regardless of which position one is in, these LP desi... » read more

DFT: Essential For Power-Aware Test


By Ann Steffora Mutschler Power-aware test is a major manufacturing consideration due to the problems of increased power dissipation in various test modes, as well as test implications that come up with the usage of various low-power design technologies. Challenges for test engineers and test tool developers include understanding the various concerns associated with power-aware test, develo... » read more

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