tag: IITC

Strategies For Faster Yield Ramps On 5nm Chips
By Laura Peters - 12 Apr, 2022 - Comments: 0

Leading chipmakers TSMC and Samsung are producing 5nm devices in high volume production and TSMC is forging ahead with plans for first 3nm silicon by year end. But to meet such aggressive targets, engineers must identify defects and ramp yield faster than before. Getting a handle on EUV stochastic defects — non-repeating patterning defects such as microbridges, broken lines, or missing con... » read more

Extending Copper Interconnects To 2nm
By Laura Peters - 17 Mar, 2022 - Comments: 0

Transistor scaling is reaching a tipping point at 3nm, where nanosheet FETs will likely replace finFETs to meet performance, power, area, and cost (PPAC) goals. A significant architectural change is similarly being evaluated for copper interconnects at 2nm, a move that would reconfigure the way power is delivered to transistors. This approach relies on so-called buried power rails (BPRs) and... » read more

Manufacturing Bits: July 10
By Mark LaPedus - 10 Jul, 2018 - Comments: 0

Ruthenium interconnects Imec has developed a process to enable ruthenium (Ru) interconnects in chips at 5nm and beyond. Ru is one of several candidates to replace traditional copper as the interconnect material in chips. The interconnects, which reside on the top of the transistor, consist of tiny copper wiring schemes that transfer electrical signals from one transistor to another. The int... » read more

Dealing With Resistance In Chips
By Mark LaPedus - 21 Jun, 2018 - Comments: 2

Chipmakers continue to scale the transistor at advanced nodes, but they are struggling to maintain the same pace with the other two critical parts of the device—the contacts and interconnects. That’s beginning to change, however. In fact, at 10nm/7nm, chipmakers are introducing new topologies and materials such as cobalt, which promises to boost the performance and reduce unwanted resist... » read more

Manufacturing Bits: June 3
By Mark LaPedus - 03 Jun, 2014 - Comments: 0

World’s thinnest TFTs The U.S. Department of Energy’s Argonne National Laboratory has devised the world’s thinnest flexible, 2D thin-film transistors (TFTs). The transistors are just 10 atomic layers thick. TFTs are typically used in screens and displays. In the lab, Argonne researchers fabricated the TFTs on both a conventional silicon platform and a flexible substrate. [caption i... » read more

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