tag: imec

Chip Industry Week in Review
By The SE Staff - 02 Aug, 2024 - Comments: 0

Okinawa Institute of Science and Technology proposed a new EUV litho technology using only four reflective mirrors and a new method of illumination optics that it claims will use 1/10 the power and cost half as much as existing EUV technology from ASML. Applied Materials may not receive expected U.S. funding to build a $4 billion research facility in Sunnyvale, CA, due to internal government... » read more

Classification and Localization of Semiconductor Defect Classes in Aggressive Pitches (imec, Screen)
By Technical Paper Link - 01 Aug, 2024 - Comments: 0

A new technical paper titled "An Evaluation of Continual Learning for Advanced Node Semiconductor Defect Inspection" was published by Imec and SCREEN SPE Germany. Abstract "Deep learning-based semiconductor defect inspection has gained traction in recent years, offering a powerful and versatile approach that provides high accuracy, adaptability, and efficiency in detecting and classifying... » read more

Key Technologies To Extend EUV To 14 Angstroms
By Laura Peters - 29 Jul, 2024 - Comments: 3

The top three foundries plan to implement high-NA EUV lithography as early as 2025 for the 18 angstrom generation, but the replacement of single exposure high-NA (0.55) over double patterning with standard EUV (NA = 0.33) depends on whether it provides better results at a reasonable cost per wafer. So far, 2024 has been a banner year for high-numerical aperture EUV lithography. Intel Foundry... » read more

Chip Industry Week In Review
By The SE Staff - 26 Jul, 2024 - Comments: 0

The U.S. Department of Commerce and Amkor Technology signed a deal to provide up to $400 million in funding, under the CHIPS and Science Act, to build a previously announced end-to-end advanced packaging plant. The combined funding is expected to total about $2 billion. The new facility will add some 2,000 jobs in Peoria, Arizona. The SK hynix Board approved its Yongin Semiconductor Cluster... » read more

Will AI Disrupt EDA?
By Brian Bailey - 25 Jul, 2024 - Comments: 1

Generative AI has disrupted search, it is transforming the computing landscape, and now it's threatening to disrupt EDA. But despite the buzz and the broad pronouncements of radical changes ahead, it remains unclear where it will have impact and how deep any changes will be. EDA has two primary roles — automation and optimization. Many of the optimization problems are NP hard, which means ... » read more

New Interconnect Metals Need New Dielectrics
By Katherine Derbyshire - 23 Jul, 2024 - Comments: 0

Just as circuit metallization must evolve to manage resistance as features shrink, so must the dielectric half of the interconnect stack. For quite some time, manufacturers have needed a dielectric constant (k) less than 4, which is the value for SiO2, but they have struggled to find materials that combine a low dielectric constant with mechanical and chemical stability. In work presented at... » read more

Multi-tier Die Stacking Through Collective Die-to-Wafer Hybrid bonding
By Brewer Science - 23 Jul, 2024 - Comments: 0

A technical paper titled "Multi-tier Die Stacking Through Collective Die-to-Wafer Hybrid bonding" was published by researchers at imec, Brewer Science and SUSS MicroTec Lithography GmbH. Abstract "A collective die-to-wafer bonding flow is extended beyond the N=2 tier to the N=3 and N=4 tier by collectively bonding multiple layers of dies on top of a target wafer. The N=2 die-level is show... » read more

Chip Industry Week In Review
By The SE Staff - 19 Jul, 2024 - Comments: 0

The University of Texas at Austin’s Texas Institute for Electronics (TIE) was awarded $840 million to establish a Department of Defense microelectronics manufacturing center. This center will focus on developing advanced semiconductor microsystems to enhance U.S. defense systems. The project is part of DARPA's NGMM Program. The U.S. Dept. of Commerce announced preliminary terms with Global... » read more

Research Bits: July 8
By Liz Allan - 08 Jul, 2024 - Comments: 0

2D TFETS for neuromorphic computing Researchers from the University of California Santa Barbara and Intel Labs used 2D transition metal dichalcogenide (TMD)-based tunnel-field-effect transistors (TFETs) in a neuromorphic computing platform, bringing the energy requirements to within two orders of magnitude (about 100 times) the amount used by the human brain. The 2D TFETs have lower off-sta... » read more

Chip Industry Week In Review
By The SE Staff - 03 Jul, 2024 - Comments: 0

Early version due to U.S. holiday. The U.S. government announced a new $504 million funding round for 12 Regional Technology and Innovation Hubs (Tech Hubs) for semiconductors, clean energy, biotechnology, AI, quantum computing, and more. Among the recipients: NY SMART I-Corridor Tech Hub (New York): $40 million for semiconductor manufacturing; Headwaters Hub (Montana): $41 million f... » read more

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