tag: imec

First Look: 5nm
By Ann Mutschler - 15 Oct, 2015 - Comments: 3

By the time the 5nm semiconductor manufacturing process node reaches mass production readiness, the hurdles and challenges will no longer be open for discussion. But as of this moment, some of them seem almost insurmountable, raising new questions about the continued viability of Moore's Law. There has been much written about the end of [getkc id="74" comment="Moore's Law"] for nearly two de... » read more

The Week In Review: Design/IoT
By Jesse Allen - 09 Oct, 2015 - Comments: 0

Imec and Cadence completed the first tapeout of a 5nm test chip. Using a processor design, the companies taped out a set of designs using EUV lithography as well as Self-Aligned Quadruple Patterning for 193i lithography, where metal pitches were scaled from the nominal 32nm pitch down to 24nm to push the limit of patterning. Tools Synopsys folded in recent acquisition Atrenta's testabilit... » read more

Manufacturing Of Next-Generation Channel Materials
By Michael Watts - 05 Oct, 2015 - Comments: 0

One of the many challenges for the IC developers is to change the channel material to increase transistor mobility. But what about manufacturing? Can LED-style epitaxy be migrated to high-volume silicon manufacturing? “The use of Ge and InGaAs quantum wells is an extension of the current strained Si strategy," said Aaron Thean, vice president of process technologies and director of the log... » read more

We Must Teach Chips To Feel Pain
By Imec - 17 Sep, 2015 - Comments: 0

By Guido Groeseneken When I was a doctorate student in the 1980s there was lots of wild speculation about Moore’s Law: give it another 10 years and transistors will stop getting smaller, they were saying back then. But in the end, the creativity of engineers turned out to be greater than the pessimism of the forecasters. Yet today I believe that we are close to the end of Moore’s Law.... » read more

EUV: Cost Killer Or Savior?
By Katherine Derbyshire - 17 Sep, 2015 - Comments: 4

Moore’s Law, the economic foundation of the semiconductor industry, states that transistor density doubles in each technology generation, at constant cost. As IMEC’s Arindam Mallik explained, however, the transition to a new technology node is not a single event, but a process. Typically, when the new technology is first introduced, it brings a 20% to 25% wafer cost increase. Process opt... » read more

Interconnect Challenges Grow
By Mark LaPedus - 20 Aug, 2015 - Comments: 1

It’s becoming apparent that traditional chip scaling is slowing down. The 16nm/14nm logic node took longer than expected to unfold. And the 10nm node and beyond could suffer the same fate. So what’s the main cause? It’s hard to pinpoint the problem, although many blame the issues on lithography. But what could eventually hold up the scaling train, and undo Moore’s Law, is arguably t... » read more

What Works After 7nm?
By Mark LaPedus - 20 Aug, 2015 - Comments: 3

An Steegen, senior vice president of process technology at [getentity id="22217" e_name="Imec"], the Belgium-based R&D organization, sat down with Semiconductor Engineering to discuss the future of process technology and transistor trends all the way to 3nm. SE: Some say the semiconductor industry is maturing. Yet we have more device types and options than ever before, right? Steegen:... » read more

Inside The 5G Smartphone
By Mark LaPedus - 20 Aug, 2015 - Comments: 3

Amid a slowdown in the cell phone business, the market is heating up for perhaps the next big thing in wireless—5th generation mobile networks or 5G. In fact, major carriers, chipmakers and telecom equipment vendors are all rushing to get a piece of the action in 5G, which is the follow-on to the current wireless standard known as 4G or long-term evolution (LTE). Intel, Samsung and Qualcom... » read more

Manufacturing Bits: August 18
By Mark LaPedus - 18 Aug, 2015 - Comments: 0

Making quantum robots Quantum dots are inorganic semiconductor nano-crystals. The technology can be used to boost the color gamut in LCD TVs. It can also be used in LEDs and other products. The problem? Quantum dots are expensive to fabricate. With funding from Dow Chemical, the University of Illinois at Urbana-Champaign has developed a new fabrication process. In doing so, researchers a... » read more

2.5D Creeps Into SoC Designs
By Ed Sperling - 13 Aug, 2015 - Comments: 0

A decade ago top chipmakers predicted that the next frontier for SoC architectures would be the z axis, adding a third dimension to improve throughput and performance, reduce congestion around memories, and reduce the amount of energy needed to drive signals. The obvious market for this was applications processors for mobile devices, and the first companies to jump on the stacked die bandwag... » read more

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