IP Becoming More Complex, More Costly

By Brian Bailey - 25 May, 2023 - Comments: 0

Success in the semiconductor intellectual property (IP) market requires more than a good bit of RTL. New advances mandate a complete design, implementation, and verification team, which limits the number of companies competing in this market. What constitutes an IP block has changed significantly since the concept was first introduced in the 1990s. What was initially just a piece of RTL (reg... » read more

Advanced RISC-V Verification Methodology Projects

By Imperas - 24 May, 2023 - Comments: 0

The open standard of RISC-V offers developers new freedoms to explore new design flexibilities and enable innovations with optimized processors. As a design moves from concept to implementation new resources are appearing to help with standards for testbenches, verification IP reuse, and coverage analysis. RISC-V offers every SoC team the possibility to design an optimized processor, but this a... » read more

Designing For In-Circuit Monitors

By Ann Mutschler - 27 Apr, 2023 - Comments: 0

In every application space the semiconductor ecosystem touches, in-circuit monitors and sensors are playing an increasing role in silicon lifecycle management and concepts around reliability and resiliency — both during design as well as in the field. The combination of true system-level design, in/on-chip monitors, and improved data analysis are expected to drastically improve reliability... » read more

RISC-V Driving New Verification Concepts

By Brian Bailey - 12 Apr, 2023 - Comments: 0

Semiconductor Engineering sat down to discuss gaps in tools and why new methodologies are needed for RISC-V processors, with Pete Hardee, group director for product management at Cadence; Mike Eftimakis, vice president for strategy and ecosystem at Codasip; Simon Davidmann, founder and CEO of Imperas Software; Sven Beyer, program manager for processor verification at Siemens EDA; Kiran Vittal, ... » read more

Do Necessary Tools Exist For RISC-V Verification?

By Brian Bailey - 30 Mar, 2023 - Comments: 0

Semiconductor Engineering sat down to discuss the verification of RISC-V processors with Pete Hardee, group director for product management at Cadence; Mike Eftimakis, vice president for strategy and ecosystem at Codasip; Simon Davidmann, founder and CEO of Imperas Software; Sven Beyer, program manager for processor verification at Siemens EDA; Kiran Vittal, senior director of alliances partner... » read more

The Race Toward Mixed-Foundry Chiplets

By Ann Mutschler - 23 Mar, 2023 - Comments: 1

Creating chiplets with as much flexibility as possible has captured the imagination of the semiconductor ecosystem, but how heterogeneous integration of chiplets from different foundries will play out remains unclear. Many companies in the semiconductor ecosystem are still figuring out how they will fit into this heterogeneous chiplet world and what issues they will need to solve. While near... » read more

Week In Review: Design, Low Power

By Jesse Allen - 17 Mar, 2023 - Comments: 0

The UK government published its National Quantum Strategy, which outlines the plan to invest £2.5 billion (~$3.0 billion) over the next 10 years into quantum technology, including computing, sensing, timing, imaging, and networking. "We will develop UK strengths across different hardware platforms, software, and components, and reinforce our capabilities throughout the supply chains. Although ... » read more

What Makes RISC-V Verification Unique?

By Brian Bailey - 09 Mar, 2023 - Comments: 0

Week In Review: Design, Low Power

By Jesse Allen - 03 Mar, 2023 - Comments: 0

Apple plans to spend an additional €1 billion (~$1.1B) over the next six years to expand its Munich, Germany-based Silicon Design Centre, including the construction of a new research facility. "The expansion of our European Silicon Design Centre will enable an even closer collaboration between our more than 2,000 engineers in Bavaria working on breakthrough innovations, including custom sil... » read more

How To Build Resilience Into Chips

By Ed Sperling and Ann Mutschler - 27 Feb, 2023 - Comments: 0

Disaggregating chips into specialized processors, memories, and architectures is becoming necessary for continued improvements in performance and power, but it's also contributing to unusual and often unpredictable errors in hardware that are extremely difficult to find. The sources of those errors can include anything from timing errors in a particular sequence, to gaps in bonds between chi... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: Imperas Software

IP Becoming More Complex, More Costly

Advanced RISC-V Verification Methodology Projects

Designing For In-Circuit Monitors

RISC-V Driving New Verification Concepts

Do Necessary Tools Exist For RISC-V Verification?

The Race Toward Mixed-Foundry Chiplets

Week In Review: Design, Low Power

What Makes RISC-V Verification Unique?

Week In Review: Design, Low Power

How To Build Resilience Into Chips