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Technical Paper Round-Up: April 19


New technical papers include selective etching, ISO 26262 test bench, hardware accelerators, RISC-V, lidar, EUV mask inspection, fault attacks, edge computing, gallium oxide, and machine learning for VLSI CAD-on-chip power grid design. Cutting-edge research is now a global effort. It extends from the U.S. Air Force, to schools such as MIT, and universities in Italy, Spain, Portugal, India, K... » read more

Machine Learning for VLSI CAD: A Case Study in On-Chip Power Grid Design


Abstract "With the improvement of VLSI technology, on-chip power grid design is becoming more challenging than before. In this design phase of VLSI CAD, power grids are generated in order to make power and ground connections to transistors or logic blocks. However, due to the scaling of supply voltage and increase in the number of transistors per unit area of the chip, power grid design has ... » read more

Machine Learning Approach for Fast Electromigration Aware Aging Prediction in Incremental Design of Large Scale On-Chip Power Grid Network


Abstract "With the advancement of technology nodes, Electromigration (EM) signoff has become increasingly difficult, which requires a considerable amount of time for an incremental change in the power grid (PG) network design in a chip. The traditional Black’s empirical equation and Blech’s criterion are still used for EM assessment, which is a time-consuming process. In this article, for ... » read more

Power/Performance Bits: Oct. 6


Waste plastic supercapacitor Researchers from the University of California Riverside found a way to recycle waste plastic into energy storage devices. The work focused on polyethylene terephthalate plastic waste, or PET, which is found in soda bottles and many other consumer products. The researchers first dissolved pieces of PET plastic bottles in a solvent. Using electrospinning, they fab... » read more

PGIREM: Reliability-Constrained IR Drop Minimization and Electromigration Assessment of VLSI Power Grid Networks using Cooperative Coevolution


Abstract "Due to the resistance of metal wires in power grid network, voltage drop noise occurs in the form of IR drop which may change the output logic of underlying circuits and may affect the reliability performance of a chip. Further, it is necessary to handle different reliability constraints while designing a robust power grid network for a chip. Any violation of such constraints may inc... » read more