Experts At The Table: Debug

By Ed Sperling - 26 Sep, 2013 - Comments: 0

By Ed Sperling Semiconductor Engineering sat down with Galen Blake, senior verification engineer at Altera; Warren Stapleton, senior fellow at Advanced Micro Devices; Stephen Bailey, director of solutions marketing at Mentor Graphics; Michael Sanie, senior director of verification marketing at Synopsys. What follows are excerpts of that conversation. SE: What are the big issues with debug? ... » read more

New Risk Factors For SoCs

By Ed Sperling - 12 Sep, 2013 - Comments: 0

By Ed Sperling Third-party IP is becoming increasingly important in SoC designs. It saves development time and adds unique value. It also can improve performance and lower power, because a company specializing in IP frequently can build and optimize it better than a company that builds entire chips. But there are also plenty of landmines in IP integration, and there is a growing concern abo... » read more

3D IC Supply Chain: Still Under Construction

By Barbara Jorgensen - 25 Jul, 2013 - Comments: 1

By Barbara Jorgensen and Ed Sperling Stacked die, which promise high levels of integration, a tiny footprint, energy conservation and blinding speed, still have some big hurdles to overcome. Cost, packaging and manufacturability continue to make steady progress, with test chips being produced by all of the major foundries. But in a disaggregated ecosystem, the supply chain remains a big st... » read more

Raising The IP Abstraction Level

By Ed Sperling - 25 Jul, 2013 - Comments: 0

By Ed Sperling An increasing reliance on commercial and re-used IP and more emphasis placed on software development is adding even more pressure onto semiconductor design teams to figure out the benefits and limitations of myriad possible choices earlier in the design process. Design teams already are under pressure to meet increasingly tighter market deadlines, and it is stressing every pa... » read more

Dealing With New Bottlenecks

By Ed Sperling - 11 Jul, 2013 - Comments: 0

By Ed Sperling While the number of options for improving efficiency and performance in designs continues to increase, the number of challenges in getting chips at advanced process nodes out the door is increasing, too. Thinner wires, routing congestion, more power domains, IP integration and lithography issues are conspiring to make design much more difficult than in the past. So why aren�... » read more

The Integrated IP Subsystem: A Converging SoC Solution

By Various Writers - 11 Jul, 2013 - Comments: 0

The consumer device market is witnessing incredible market space convergence between mobile handheld, automotive, and home electronics. IP vendors, engineers, and system design engineers face a multitude of challenges when designing and developing ICs, systems, or subsystems for the next great portable device. The next cell phone for instance, will not only be a multimedia player, but also a de... » read more

Faster IP Integration

By Ed Sperling - 03 Jul, 2013 - Comments: 0

By Ed Sperling System-Level Design sat down with Laurent Moll, chief technology officer at Arteris, to talk about interoperability, complexity and integration issues. What follows are excerpts of that conversation. SLD: What’s the big challenge with IP? Moll: Interoperability is always a concern. Because of ARM’s dominance, a lot of people are moving to AMBA protocols, whether that’... » read more

Experts At The Table: Performance Analysis

By Ed Sperling - 28 Jun, 2013 - Comments: 0

Low-Power/High-Performance Engineering sat down with Ravi Kalyanaraman, senior verification manager for the digital entertainment business unit at Marvell; William Orme, strategic marketing manager for ARM’s System IP and Processor Division; Steve Brown, product marketing and business development director for the systems and software group at Cadence; Johannes Stahl director of product market... » read more

Drowning In Data

By Ed Sperling - 13 Jun, 2013 - Comments: 0

By Ed Sperling The old adage, “Be careful what you wish for,” has hit the SoC design market like a 100-year storm. After years of demanding more data to understand what’s going on in a design, engineering teams now have so much data that they’re drowning in it. This is most obvious at advanced process nodes, of course. But it’s also true these days at more mainstream nodes such as... » read more

The X Factor

By Ed Sperling - 30 May, 2013 - Comments: 0

By Ed Sperling The number of unknowns is growing in every segment of SoC design all the way through manufacturing, raising the stakes between reliability and the tradeoffs necessary to meet market windows. Tools are available to deal with some of these unknowns, or X’s, but certainly not all of them. Moreover, no single tool can handle all unknowns, some of which can build upon other unkn... » read more

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Knowledge Centers
Entities, people and technologies explored

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3.5D: The Great Compromise

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The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

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Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

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Megafabs churning out the most advanced processors are not the only game in town.

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tag: integration