Chip Industry Week In Review

By The SE Staff - 29 Mar, 2024 - Comments: 0

By Adam Kovac, Karen Heyman, and Liz Allan. China introduced strict procurement guidelines aimed at blocking the use of AMD and Intel processors in government computers. Meanwhile, China urged the Netherlands to ease restrictions on deep ultraviolet (DUV) litho equipment, according to Nikkei Asia. DUV is an older technology, based on 193nm ArF lasers, but in conjunction with multi-p... » read more

Interconnects Essential To Heterogeneous Integration

By Karen Heyman - 28 Mar, 2024 - Comments: 0

Designing and manufacturing interconnects is becoming more complex, and more critical to device reliability, as the chip industry shifts from monolithic planar dies to collections of chips and chiplets in a package. What was once as simple as laying down a copper trace has evolved into tens of thousands of microbumps, hybrid bonds, through-silicon vias (TSVs), and even junctions for optical ... » read more

Chip Industry Week In Review

By The SE Staff - 22 Mar, 2024 - Comments: 0

By Adam Kovac, Gregory Haley, and Liz Allan. The U.S. government released a 61-page report, titled "National Strategy on Microelectronics Research,” by the Subcommittee On Microelectronics Leadership. It provides a framework for government, industry, academia, and international allies to address four major goals. Synopsys acquired Intrinsic ID, which develops physical unclonable func... » read more

Digital Twins Target IC Tool And Fab Efficiency

By Laura Peters - 21 Mar, 2024 - Comments: 0

Digital twins have emerged as the hot "new" semiconductor manufacturing technology, enabling fabs to create a virtual representation of a physical system on which to experiment and optimize what's going on inside the real fab. While digital twin technology has been in use for some time in other industries, its use has been limited in semiconductor manufacturing. What's changing is the breadt... » read more

Powering CFETs From The Backside

By Katherine Derbyshire - 21 Mar, 2024 - Comments: 0

The first CMOS circuits to incorporate backside power connections are likely to be based on stacked nanosheet transistors, but further down the road, planners envision complementary transistors (CFETs) that vertically integrate stacked NFET and PFET devices. With at least twice the thickness of a nanosheet transistor, connecting CFETs to each other and to the rest of the circuit is likely to... » read more

Chip Industry Technical Paper Roundup: Mar. 19

By Linda Christensen - 19 Mar, 2024 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library. [table id=206 /] More ReadingTechnical Paper Library home » read more

Optimizing Energy At The System Level

By Brian Bailey - 18 Mar, 2024 - Comments: 0

Power is a ubiquitous concern, and it is impossible to optimize a system's energy consumption without considering the system as a whole. Tremendous strides have been made in the optimization of a hardware implementation, but that is no longer enough. The complete system must be optimized. There are far reaching implications to this, some of which are driving the path toward domain-specific c... » read more

Backside Power Delivery Adds New Thermal Concerns

By Karen Heyman - 14 Mar, 2024 - Comments: 0

As the semiconductor industry gears up for backside power delivery at the 2nm node, implementation of the technology requires a re-thinking of established design practices. While some EDA tools are already qualified, designers must acquaint themselves with new issues, including making place-and-route more thermal-aware and how to manage heat dissipation with less shielding and thinner substr... » read more

UCIe-3D: SiP Architectures With Advanced 3D Packaging With Shrinking Bump Pitches (Intel)

By Technical Paper Link - 12 Mar, 2024 - Comments: 0

A technical paper titled “High-performance, power-efficient three-dimensional system-in-package designs with universal chiplet interconnect express” was published by researchers at Intel. Abstract: "Universal chiplet interconnect express (UCIe) is an open industry standard interconnect for a chiplet ecosystem in which chiplets from multiple suppliers can be packaged together. The UCIe 1.0... » read more

DTCO/STCO Create Path For Faster Yield Ramps

By Laura Peters - 12 Mar, 2024 - Comments: 0

Higher density in planar SoCs and advanced packages, coupled with more complex interactions and dependencies between various components, are permitting systematic defects to escape traditional detection methods. These issues increasingly are not detected until the chips reach high-volume manufacturing, slowing the yield ramp and bumping up costs. To combat these problems, IDMs and systems co... » read more

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tag: Intel

Chip Industry Week In Review

Interconnects Essential To Heterogeneous Integration

Chip Industry Week In Review

Digital Twins Target IC Tool And Fab Efficiency

Powering CFETs From The Backside

Chip Industry Technical Paper Roundup: Mar. 19

Optimizing Energy At The System Level

Backside Power Delivery Adds New Thermal Concerns

UCIe-3D: SiP Architectures With Advanced 3D Packaging With Shrinking Bump Pitches (Intel)

DTCO/STCO Create Path For Faster Yield Ramps

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