tag: Intel

Chip Industry Technical Paper Roundup: Mar. 19
By Linda Christensen - 19 Mar, 2024 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library. [table id=206 /] More ReadingTechnical Paper Library home » read more

Optimizing Energy At The System Level
By Brian Bailey - 18 Mar, 2024 - Comments: 0

Power is a ubiquitous concern, and it is impossible to optimize a system's energy consumption without considering the system as a whole. Tremendous strides have been made in the optimization of a hardware implementation, but that is no longer enough. The complete system must be optimized. There are far reaching implications to this, some of which are driving the path toward domain-specific c... » read more

Backside Power Delivery Adds New Thermal Concerns
By Karen Heyman - 14 Mar, 2024 - Comments: 0

As the semiconductor industry gears up for backside power delivery at the 2nm node, implementation of the technology requires a re-thinking of established design practices. While some EDA tools are already qualified, designers must acquaint themselves with new issues, including making place-and-route more thermal-aware and how to manage heat dissipation with less shielding and thinner substr... » read more

UCIe-3D: SiP Architectures With Advanced 3D Packaging With Shrinking Bump Pitches (Intel)
By Technical Paper Link - 12 Mar, 2024 - Comments: 0

A technical paper titled “High-performance, power-efficient three-dimensional system-in-package designs with universal chiplet interconnect express” was published by researchers at Intel. Abstract: "Universal chiplet interconnect express (UCIe) is an open industry standard interconnect for a chiplet ecosystem in which chiplets from multiple suppliers can be packaged together. The UCIe 1.0... » read more

DTCO/STCO Create Path For Faster Yield Ramps
By Laura Peters - 12 Mar, 2024 - Comments: 0

Higher density in planar SoCs and advanced packages, coupled with more complex interactions and dependencies between various components, are permitting systematic defects to escape traditional detection methods. These issues increasingly are not detected until the chips reach high-volume manufacturing, slowing the yield ramp and bumping up costs. To combat these problems, IDMs and systems co... » read more

Strategies For Detecting Sources Of Silent Data Corruption
By Anne Meixner - 12 Mar, 2024 - Comments: 0

Engineering teams are wrestling with how to identify the root causes of silent data corruption (SDC) in a timely and cost-effective way, but the solutions are turning out to be broader and more complex than simply fixing a single defect. This is particularly vexing for data center reliability, accessibility and serviceability (RAS) engineering teams, because even the best tools and methodolo... » read more

Chip Industry Week In Review
By The SE Staff - 01 Mar, 2024 - Comments: 0

By Adam Kovac, Karen Heyman, and Liz Allan. India approved the construction of two fabs and a packaging house, for a total investment of about $15.2 billion, according to multiple sources. One fab will be jointly owned by Tata and Taiwan's Powerchip. The second fab will be a joint investment between CG Power, Japan's Renesas Electronics, and Thailand's Stars Microelectronics. Tata will run t... » read more

Accellera Preps New Standard For Clock-Domain Crossing
By Brian Bailey - 29 Feb, 2024 - Comments: 0

Part of the hierarchical development flow is about to get a lot simpler, thanks to a new standard being created by Accellera. What is less clear is how long will it take before users see any benefit. At the register transfer level (RTL), when a data signal passes between two flip flops, it initially is assumed that clocks are perfect. After clock-tree synthesis and place-and-route are perfor... » read more

Integration Challenges For RISC-V Designs
By Ed Sperling - 27 Feb, 2024 - Comments: 0

One of the big draws of RISC-V is that it allows design teams to create unique chips or chiplets and to make modifications to the instruction-set architecture. That extra degree of freedom also creates some issues when it comes to integrating those designs into packages or systems because they may require non-standard connectivity approaches. Frank Schirrmeister, vice president of marketing at ... » read more

Thinking Big: From Chips To Systems
By Ed Sperling - 27 Feb, 2024 - Comments: 0

Semiconductor Engineering sat down with Aart de Geus, executive chair and founder of Synopsys, to talk about the shift from chips to systems, next-generation transistors, and what's required to build multi-die devices in the context of rapid change and other systems. SE: What are the biggest changes you're seeing in the chip industry these days, and why now? de Geus: It's not just the siz... » read more

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