Chip Industry Technical Paper Roundup: May 7

Heterogeneous multi-processor SoCs; parallel RTL simulation; GaN micro-light emitting transistor; cryo-CMOS voltage references; early anomaly detection in auto SoCs; metrology for 2D materials; practical Rowhammer fingerprinting.


New technical papers added to Semiconductor Engineering’s library this week.

Technical Paper Research Organizations
Optimizing Offload Performance in Heterogeneous MPSoCs ETH Zurich
Parendi: Thousand-Way Parallel RTL Simulation EPFL
Tunnel Junction-Enabled Monolithically Integrated GaN Micro-Light Emitting Transistor Ohio State University and Sandia National Laboratory
Cryo-CMOS Voltage References for the Ultrawide Temperature Range From 300 K Down to 4.2 K Delft University of Technology, QuTech, Kavli Institute of Nanoscience Delft, and EPFL
Enhancing Functional Safety in Automotive AMS Circuits through Unsupervised Machine Learning UT Dallas, Intel, NXP, and TI
Metrology for 2D materials: a perspective review from the international roadmap for devices and systems Arizona State University, IBM Research, Unity-SC, and NIST
Centauri: Practical Rowhammer Fingerprinting UC Davis

More Reading
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