Fundamental Changes In Economics Of Chip Security


Protecting chips from cyberattacks is becoming more difficult, more expensive and much more resource-intensive, but it also is becoming increasingly necessary as some of those chips end up in mission-critical servers and in safety-critical applications such as automotive. Security has been on the semiconductor industry's radar for at least the past several years, despite spotty progress and ... » read more

Designing The Next Big Things


The edge is a humongous opportunity for the semiconductor industry. The problem, despite its name, is that it's not a single thing. It will be comprised of thousands of different chips and systems, and very few will be sold in large volumes. The edge is the culmination of decades of improvement in power and performance, coupled with the architectural creativity that has exploded since the bene... » read more

Data Strategy Shifting Again In Cars


Carmakers are modifying their data processing strategies to include more processing at or near the source of data, reducing the amount of data that needs to be moved around within a vehicle to both improve response time and free up compute resources. These moves are a world away from the initial idea that terabytes of streaming data would be processed in the cloud and sent back to the vehicl... » read more

Power/Performance Bits: June 2


Neuromorphic memristor Researchers at the University of Massachusetts Amherst used protein nanowires to create neuromorphic memristors capable of running at extremely low voltage. A challenge to neuromorphic computing is mimicking the low voltage at which the brain operates: it sends signals between neurons at around 80 millivolts. Jun Yao, an electrical and computer engineering researcher at ... » read more

The Good And Bad Of Chiplets


The chiplet model continues to gain traction in the market, but there are still some challenges to enable broader support for the technology. AMD, Intel, TSMC, Marvell and a few others have developed or demonstrated devices using chiplets, which is an alternative way to develop an advanced design. Beyond that, however, the adoption of chiplets is limited in the industry due to ecosystem issu... » read more

Latest IC Outlook: More Uncertainty


So far in 2020, it’s been a difficult period in the semiconductor industry amid the Covid-19 pandemic outbreak and other issues. And heading into the second half of 2020, the industry faces more challenges, if not uncertainty, in the market. Many segments in the semiconductor industry face some headwinds, but there might be some positive news in the equipment business. To be sure,... » read more

Week In Review: Auto, Security, Pervasive Computing


Edge, cloud, data center Cadence added new verification IP (VIP) for hyperscalar data centers that supports CXL – Compute Express Link, HBM3, and Ethernet 802.3ck. The VIP are part of Cadence’s Verification Suite. Cadence also released IP for 56G long-reach SerDes on TSMC’s N7 and N6 process technologies. Many Mentor, a Siemens Business, IC design tools are now certified TSMC’s N5 a... » read more

Spiking Neural Networks: Research Projects or Commercial Products?


Spiking neural networks (SNNs) often are touted as a way to get close to the power efficiency of the brain, but there is widespread confusion about what exactly that means. In fact, there is disagreement about how the brain actually works. Some SNN implementations are less brain-like than others. Depending on whom you talk to, SNNs are either a long way away or close to commercialization. Th... » read more

Week In Review: Manufacturing, Test


Chipmakers TSMC has announced its intention to build and operate an advanced semiconductor fab in the U.S. The fab, to be built in Arizona, will utilize TSMC’s 5nm technology and will produce 20,000 wafers per month. TSMC’s total spending on this project will be approximately $12 billion from 2021 to 2029. Construction is planned to start in 2021 with production targeted to begin in 202... » read more

‘More Than Moore’ Reality Check


The semiconductor industry is embracing multi-die packages as feature scaling hits the limits of physics, but how to get there with the least amount of pain and at the lowest cost is a work in progress. Gaps remain in tooling and methodologies, interconnect standards are still being developed, and there are so many implementations of packaging that the number of choices is often overwhelming. ... » read more

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