5nm Vs. 3nm

By Mark LaPedus - 24 Jun, 2019 - Comments: 16

Foundry vendors are readying the next wave of advanced processes, but their customers will face a myriad of confusing options—including whether to develop chips at 5nm, wait until 3nm, or opt for something in between. The path to 5nm is well-defined compared with 3nm. After that, the landscape becomes more convoluted because foundries are adding half-node processes to the mix, such as 6nm ... » read more

Telle Whitney Receives IEEE Honorary Membership

By Ann Mutschler - 22 Jun, 2019 - Comments: 0

On May 17 Telle Whitney received the 2019 IEEE Honorary Membership at the 2019 IEEE Vision, Innovation, and Challenges Summit (IEEE VIC Summit) in San Diego for leadership in supporting and promoting women in technology, and for building a highly impactful global organization dedicated to this purpose. Sponsored by IEEE, the grade of Honorary Member is a significant honor bestowed by IEEE a... » read more

Falling Chip Forecasts

By Mark LaPedus - 20 Jun, 2019 - Comments: 1

It’s time to take a pulse of the semiconductor market amid the memory downturn and trade frictions with China. For some time, the DRAM and NAND markets have been hit hard with falling prices and oversupply. Then, the Trump administration last year slapped tariffs on Chinese goods. China retaliated. And the trade war rages on between the U.S. and China. More recently, the U.S. Department... » read more

Sidestepping Moore’s Law

By Mark LaPedus - 20 Jun, 2019 - Comments: 2

Calvin Cheung, vice president of engineering at ASE, sat down with Semiconductor Engineering to talk about advanced packaging, the challenges involved with the technology, and the implications for Moore’s Law. What follows are excerpts of that conversation. SE: What are some of the big issues with IC packaging today? Cheung: Moore’s Law is slowing down, but transistor scaling will co... » read more

Improvement Of Dopant Concentration Control With Acoustic Control System For B-SiGe Epitaxy Deposition

By Veeco - 19 Jun, 2019 - Comments: 0

Currently, SiGe-B epitaxy is a leading technology to induce strain in PMOS channel and improve the hole mobility to achieve better device performance. In practice, we observe that the device performance strongly depends on the dopant concentration, especially boron concentration. It is shown that the Acoustic Control System [ACS] is able to actively respond to instantaneous variations of incomi... » read more

Week In Review: Manufacturing, Test

By Mark LaPedus - 14 Jun, 2019 - Comments: 0

Market research In the second quarter of 2019, TrendForce said that the top-5 foundry rankings remained identical with that of last year. But sixth to tenth place showed some changes. Who is up or down in what is a tough business climate? Global fab equipment spending will rebound in 2020, growing 20% to $58.4 billion after dropping 19% to $48.4 billion in 2019, according to SEMI. However, ... » read more

Week in Review: IoT, Security, Auto

By Jeff Dorsch - 14 Jun, 2019 - Comments: 0

Products/Services Mentor, a Siemens Business, announced the release of the final phase of the Valor software New Product Introduction design-for-manufacturing technology, automating printed circuit board design reviews. The company has integrated DFM technology into the Xpedition software layout application. Arteris IP reports that Toshiba has taped out its next-generation advanced driv... » read more

Week In Review: Design, Low Power

By Jesse Allen - 14 Jun, 2019 - Comments: 0

M&A Intel will acquire Barefoot Networks, a maker of programmable Ethernet switch silicon and the P4 networking programming language for data centers. Founded in 2013, the Santa Clara-based company has raised $155.4 million in funding. Terms of the deal were not disclosed, but Intel expects the acquisition to be final in the third quarter of this year. Tools & IP Mentor extended it... » read more

Waiting For Chiplet Interfaces

By Brian Bailey - 13 Jun, 2019 - Comments: 0

There aren't many success stories related to chiplets today for a very simple reason—there are few standard interfaces defined for how to connect them. In fact, the only way to use them is to control both sides of the interface with a proprietary interface and protocol. The one exception is the definition of HBM2, which enables large quantities of third-party DRAM to be connected to a logi... » read more

Data Confusion At The Edge

By Ed Sperling - 11 Jun, 2019 - Comments: 0

Disparities in pre-processing of data at the edge, coupled with a total lack of standardization, are raising questions about how that data will be prioritized and managed in AI and machine learning systems. Initially, the idea was that 5G would connect edge data to the cloud, where massive server farms would infer patterns from that data and send it back to the edge devices. But there is far... » read more

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tag: Intel

5nm Vs. 3nm

Telle Whitney Receives IEEE Honorary Membership

Falling Chip Forecasts

Sidestepping Moore’s Law

Improvement Of Dopant Concentration Control With Acoustic Control System For B-SiGe Epitaxy Deposition

Week In Review: Manufacturing, Test

Week in Review: IoT, Security, Auto

Week In Review: Design, Low Power

Waiting For Chiplet Interfaces

Data Confusion At The Edge

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