tag: interposer

Is Design Innovation Slowing?
By Brian Bailey - 10 Aug, 2017 - Comments: 0

Paul Teich, principal analyst for Tirias Research, gave a provocative talk at the recent DAC conference entitled, "Is Integration Leaving Less Room for Design Innovation?" The answer isn't as simple as the question might suggest. "Integration used to be a driver for increasing the functionality of silicon," Teich said. "Increasingly, it will be used to incorporate more features of an entire ... » read more

Challenges For Future Fan-Outs
By Mark LaPedus - 07 Jul, 2017 - Comments: 1

The fan-out wafer-level packaging market is heating up. At the high end, for example, several packaging houses are developing new fan-out packages that could reach a new milestone and hit or break the magic 1µm line/space barrier. But the technology presents some challenges, as it may require more expensive process flows and equipment like lithography. Fig. 1: Redistribution layers. Source: L... » read more

Intel Inside The Package
By Ed Sperling - 08 May, 2017 - Comments: 1

Mark Bohr, senior fellow and director of process architecture and integration at Intel, sat down with Semiconductor Engineering to discuss the growing importance of multi-chip integration in a package, the growing emphasis on heterogeneity, and what to expect at 7nm and 5nm. What follows are excerpts of that interview. SE: There’s a move toward more heterogeneity in designs. Intel clearly ... » read more

Biz Talk: ASICs
By Ed Sperling - 27 Mar, 2017 - Comments: 0

eSilicon CEO [getperson id="11145" comment="Jack Harding"] talks about the future of scaling, advanced packaging, the next big things—automotive, deep learning and virtual reality—and the need for security. [youtube vid=leO8gABABqk]   Related Stories Executive Insight: Jack Harding (Aug 2016) eSilicon’s CEO looks at industry consolidation, competition, China’s impact, an... » read more

Betting On Wafer-Level Fan-Outs
By Ed Sperling - 06 Feb, 2017 - Comments: 2

Advanced packaging is starting to gain traction as a commercially viable business model rather than just one more possible option, propelled by the technical difficulties in routing signals at 10nm and 7nm and skyrocketing costs of device scaling on a single die. The inclusion of a [getkc id="202" kc_name="fan-out"] package for logic in Apple's iPhone 7, based on TSMC's Integrated Fan-Out (... » read more

Noise Killed My Chip
By Brian Bailey - 08 Sep, 2016 - Comments: 0

In the past, noise was considered an annoyance, especially for analog circuitry. But today chips are actually failing because insufficient analysis was performed. Noise types that used to be second-order effects are becoming primary factors that have to be considered. This is happening at the same time that noise margins are getting smaller, both in the amplitude and temporal dimensions. It ... » read more

Designing SoC Power Networks
By Brian Bailey - 11 Aug, 2016 - Comments: 0

Designing a power network for a complex SoC is becoming critical for the success of the product, but most chips are still using old techniques that are ill-suited to the latest fabrication technologies, resulting in an expensive, overdesigned product. Not only is the power network as designed too large, but this has several knock-on effects that impact area, timing and power. In the first pa... » read more

Electromigration: Not Just Copper Anymore
By Katherine Derbyshire - 31 May, 2016 - Comments: 2

While integrated circuit manufacturers have worried about electromigration for a long time, until recently most of their concerns have focused on the on-chip interconnects. The larger dimensions found in integrated circuit packages have, in most cases, improved heat dissipation, reduced current density, and eliminated most [getkc id="160" kc_name="electromigration"] risks. Over the last sev... » read more

2.5D Becomes A Reality
By Ed Sperling - 11 May, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss 2.5D and advanced packaging with Max Min, senior technical manager at [getentity id="22865" e_name="Samsung"]; Rob Aitken, an [getentity id="22186" comment="ARM"] fellow; John Shin, vice president at [getentity id="22903" e_name="Marvell"]; Bill Isaacson, director of ASIC marketing at [getentity id="22242" e_name="eSilicon"]; Frank Ferro, senior di... » read more

Is The 2.5D Supply Chain Ready?
By Ed Sperling - 28 Sep, 2015 - Comments: 0

A handful of big semiconductor companies began taking the wraps off 2.5D and fan-out packaging plans in the past couple of weeks, setting the stage for the first major shift away from Moore's Law in 50 years. Those moves coincide with reports of commercial [getkc id="82" kc_name="2.5D"] chips from chip assemblers and foundries that are now under development. There have been indications for... » read more

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