Noise Killed My Chip

Which kind of noise is likely to give your next project a headache, and what you can do about it.


In the past, noise was considered an annoyance, especially for analog circuitry. But today chips are actually failing because insufficient analysis was performed.

Noise types that used to be second-order effects are becoming primary factors that have to be considered. This is happening at the same time that noise margins are getting smaller, both in the amplitude and temporal dimensions. It normally takes a significant failure within the industry before things change, and the word on the street is that such a failure has happened—and that many companies are now paying a lot more attention to noise analysis.

There are no new sources of noise and yet “noise has become one of the most critical issues in semiconductors,” says Mick Tegethoff, director of product marketing for analog/mixed-signal verification at Mentor Graphics. “It impacts analog circuits, it impacts digital circuits.”

While there may be no new sources, the problem is getting worse. “There are a couple of reasons,” says Eric Naviasky, fellow in the design IP group of Cadence. “First, we have higher density of switching currents per square millimeter than we had in the past. This is directly due to process scaling. The density of decoupling capacitors has not been able to keep up. In addition, di/dt has increased. The processes are faster and thus for all of the inductive components, di/dt affects you. In the past, you did not need to worry about every picoHenry, but today you worry about everything.”

The tolerance to noise is decreasing. “We believe that the lower you go in geometry, the bigger the problem will become,” says Tegethoff. “You have less headroom in the voltage level, the data rates keep going up, and circuits need to be low power.”

To get a handle on noise, you first have to understand all of the sources. “Major sources of noise fall into two broad categories, device physics and manufacturing related vs. environment related,” says Brian Chen, mixed-signal product marketing manager at Synopsys. “The former includes device-level thermal noise, shot noise, induced gate noise, flicker noise and random telegraph noise, whereas the latter includes substrate noise and simultaneous switching output noise.”

Device noise is the one that people have to become more familiar with. “As people go into the nanometer technologies, noise sources that in the past were second- or third-order effects have become first-order effects—in particular, thermal noise and flicker noise in the transistors,” explains Tegethoff. “

Flicker noise has been getting noticeably worse as device technology is being scaled. “It also exhibits significant variation from device to device,” says Chen. “The effect of flicker noise on analog circuits’ performance is significant not only in low frequencies, but may also be critical in high frequencies, such as on phase noise of oscillators through up-conversion.”

FinFET noise
FinFETs have been an integral part of the technology scaling race. “Their ability to operate at very low voltages, yet having low leakage characteristics, have made them the standard architecture for the foreseeable CMOS future,” says Arvind Shanmugavel, senior director for applications engineering at Ansys. “These advantages, however, come with a price — power noise. On one hand, finFET devices in 10nm or 7nm can now reliable operate down to 500mV supply voltage (Vsupply) range. On the other hand, the threshold voltage (Vt) has not changed much for these technology nodes. The margin of operation Vsupply – Vt has drastically decreased and designers need to pay special attention to power supply noise variations.”

But the finFETs themselves may have made things worse. “FinFETs raised the temperature, which increases the white noise,” says Jerry Zhao, director of product marketing for power signoff at Cadence. “In the local area, temperature is higher because the 3D fin structure of the device traps heat, and that heat goes vertically to the routing layers that are on top of those devices. That increase in temperature increases the noise.”

Naviasky adds that “the finFET structure also does not give us nice a decap, so the ability to clean it up is not there. Some processes have memcaps, but they have another set of problems associated with them. It is not that finFETs brought us new noise. It is just that they exacerbated the previous problem and hurt us on the decap.”

And as with many things at these dimensions, problems start to become interrelated. “While self-heating can be pretty bad, it is a double whammy when the electromigration (EM) problem also hits you,” continues Naviasky. “Our rule of thumb is that we don’t allow self-heating to be more than 5 degrees otherwise the EM will bite you first, before the noise bites you.”

Environmental noise
Environment-related noise sources stem from switching of nearby digital circuits or components that produce voltage fluctuations in power rails.

“As transistor packing density keeps going up with newer technologies and communication bit-rates gets higher, the magnitude of such noise sources has been on the rise,” says Chen. “Circuit designers need advanced simulation capabilities, such as spurious phase-noise analysis and power integrity-aware statistical eye analysis, to efficiently predict the impact of environment-related noise. Designs using FD-SOI or finFET-on-SOI technologies may be less prone to such noises thanks to higher resistivity of the buried oxide layer than that of silicon substrate.”

With supply voltage being lower and an increase of frequency, current densities can increase, and that generates noise on the power grid. “That is what people normally mean by IR drop,” says Zhao. “That large switching current will definitely impact anything that is coupled to it, and that means the analog circuitry. People try to isolate them by moving them away, or using an LDO regulator or even a separate power network, but they can still be coupled through the substrate. So the analog is affected by the digital switching in addition to the analog noise generated by the circuit itself.”

Shanmugavel agrees. “Designs that have a mixture of analog and digital components need to pay careful attention to the coupling of noise from the digital to sensitive analog components. Shared power and ground domains are noise pathways that can couple noise and cause issues during operation. Substrate noise injection is especially important to simulate for RF components integrated along with high-speed digital cores.”

There are many new packaging options becoming available today that can help with noise, but all of them require additional analysis. “A lot of self-induced noise is related to packaging,” says Naviasky. “This is where a design picks up the large common inductances. This is also the place where all of the digital currents mix with the analog current and wiggle the ground. Some people are doing 2.5D, and the interposer gives you another degree of freedom. You can do a better job at keeping common inductance down. LDOs will protect one side, which is Vdd, but ground tends to be mixed together. And any analog circuit, or even a digital circuit, that has to live next to a DDR I/O knows the pain of ground current.”

In order to meet the operational requirements for an SoC, designers have to drastically improve the noise simulation across multiple fronts. “In the past, power noise simulations were done in silos,” says Shanmugavel. “The chip designer, package designer and the board designer would have individual supply noise budgets to meet. As long as they were within their budgets, the overall operation of the chip was guaranteed. With the diminishing noise margins in advanced technology nodes, the silo-based margining quickly leads to over-design. Having a comprehensive co-simulation of the chip, package and board is mandatory in these technology nodes.”

Zhao puts a figure on this. “If you don’t simulate the package attached to your die, then you may find the hotspots, but the absolute values could be up to 20% off.”

New packaging technologies have enabled highly integrated, heterogeneous multi-chip modules. Various components and chips in a module or package frequently are produced with distinctly different technologies, often by different technology vendors that do not necessarily coordinate their design kits. “There are challenges with this, and noise is one of them,” says Tegethoff. “You have high data-rate transfers between them and jitter is critical. This is the phase noise of the circuit.”

With those high data-rates, crosstalk can become a problem. “We are good at keeping the crosstalk down on the chip, but once you get into the 3D structure of the package, crosstalk becomes a much bigger issue,” adds Naviasky. “We try and keep it 55dB down between the aggressors and any of the victims. The package is the number one offender for raising the crosstalk floor. That is technically another noise.”

When pieces of the package come from several sources, it can create problems. “As designers try to predict the in-situ characteristics of their designs, including noise characteristics, as part of a package, it is important that the circuit simulator handles a multitude of design kits smoothly and properly resolves cross-kit conflicts,” says Chen.

To understand how significant noise is becoming, Mentor’s Tegethoff relayed two pieces of analysis. “The first was conducted by Boris Murmann at Stanford. He concluded that for high precision ADCs, as used in wireless transceivers implemented in nanometer geometries, the device noise effects become the primary limiter in performance rather than just quantization effects, which were the limit in the past.”

The second analysis was a case study they conducted with Qualcomm. “They used transient noise analysis, which includes thermal and flicker noise of the transistors, and were able to show a 25dB difference in response compared to regular transient simulation,” he says. “This matched the results of silicon.”

Noise may not a problem everywhere yet. “It is very circuit-dependent,” continues Tegethoff. “There are classes of circuits that are critical to the applications and that are very sensitive to these particular noise sources.”

One such class of circuits is PLLs. They are used in digital chips for clocking, as well as in the synthesizers for wireless transceivers. They also are inside of most SerDes. The key challenge is jitter and meeting the jitter spec at the target data rate.

Environmental noise can have far-reaching impact, too. “When you have voltage supply noise, even a digital instance is not ideal anymore,” says Zhao. “The voltage drop impact on static timing has become more severe. The design community and EDA have to come up with better solutions for this. How does the variation of voltage distribution on the die impact timing, which means performance? We have good solutions for clock jitter analysis, which is more specifically a timing issue, but now we have to consider this new angle.”

Naviasky puts this into perspective. “The drop at a particular gate caused by switching can easily be 100mV. Think about the propagation numbers and how much they change for 100mV. That is huge. You would have to close timing again if you were told the power supply was changing by 100mV. That is happening randomly in the background. It is a big deal. You have to be more conservative by a very large margin.”

Dealing with noise
Analog is arguably the canary in the coal mine. “The people who take care of it have been struggling with it for so long that it is just part of their job description,” says Naviasky. “However, the digital guys have lived in this beautiful abstraction for so long, where noise was not that big of a deal. Now they are being confronted with it. Still, they have noise margins that analog designers cannot even dream of.”

Both foundries and circuit designers have been trying to mitigate the impact of flicker noise by taking advantage of its physical nature, i.e. the charge trapping and de-trapping process.

“Foundries have been trying to perfect fabrication techniques such as those related to surface preparation and cleaning that result in higher surface quality and thus lower flicker noise,” says Synopsys’ Chen. “Design techniques to mitigate flicker noise include chopping, correlated double sampling, and switched biasing. The switched biasing technique, which effectively cycles a MOS transistor between strong inversion and accumulation, leads to much lower flicker noise in a fashion similar to the recovery phenomenon of the bias-temperature instability (BTI) effect.”

Circuit designers also are becoming more aware of the problem. “The approaches used in the past continue to work but designers have had to adapt to the device noise problem,” says Tegethoff. “To help minimize it, they have to include it in the simulation. Without including it they will have problems that result in respins.”

And today, it is in analysis where the biggest advances are being made. “The good news is that finFETs came after the foundries started doing a better job of modeling 1/f noise,” says Naviasky. “They are producing better models rather than ignoring them, as they had in the past. Now we have good correlation between noise models and silicon.”

All of the vendors have been beefing up their tools that provide noise analysis and making the technology much more accessible than it was in the past. But no tool can do everything in this area.

“Noise is random,” said Tegethoff. “Random behavior means you have to have the right stochastics and mathematics behind it, and it has to be truly random. Then you have to know how long you need to run for the randomness to bear out otherwise you get inaccurate results.”

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