Why IP Subsystems And Why Now?

By Rich Wawrzyniak - 23 Jun, 2016 - Comments: 0

At the recently concluded DAC 2016 conference in Austin, Texas, I had the opportunity to participate in a tutorial on IP Subsystems on Wednesday the 8th. Also participating were Marco Brambilla, Director of Engineering at Synapse Design and Drew Wingard, CTO at Sonics. The reality today is that device complexity in many applications has risen to levels that require increasing amounts of disc... » read more

IP Subsystems: What Works, What Doesn’t

By Ann Mutschler - 21 Aug, 2014 - Comments: 0

The [getkc id="81" kc_name="SoC"] landscape has changed substantially over the past decade and so have some of the definitions for aspects of the system—particularly the [getkc id="43" kc_name="IP"] subsystem. “We’ve been at the point for some time for large SoCs that what we thought about as a building block 10 years ago is now too small,” said [getperson id="11489" p_name="Drew Win... » read more

The Integrated IP Subsystem: A Converging SoC Solution

By Various Writers - 15 Jan, 2014 - Comments: 0

The consumer device market is witnessing incredible market space convergence between mobile handheld, automotive, and home electronics. IP vendors, engineers, and system design engineers face a multitude of challenges when designing and developing ICs, systems, or subsystems for the next great portable device. The next cell phone for instance, will not only be a multimedia player, but also a ... » read more

Experts At The Table: Next-Generation IP Landscape

By Ann Mutschler - 13 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler System-Level Design sat down to discuss predictions about the next generation design IP landscape with Robert Aitken, R&D fellow at ARM; Laurent Moll, chief technical officer at Arteris; Susan Peterson, group director, product marketing for verification IP & memory models in the system & software realization group at Cadence; and John Koeter, vice preside... » read more

Experts At The Table: Next-Generation IP Landscape

By Ann Mutschler - 22 Aug, 2013 - Comments: 0

Pitfalls In Subsystem Reuse

By Ann Mutschler - 30 May, 2013 - Comments: 0

By Ann Steffora Mutschler IP subsystems provide a ‘divide and conquer’ approach to SoC design by combining multiple IP blocks together to perform individual functions such as audio, graphics or video. The advantage of this approach is that these functions can be tested and verified at the unit level then integrated with the top-level SoC. This also facilitates reuse because each of ... » read more

Version Control

By Ed Sperling - 14 Mar, 2013 - Comments: 0

By Ed Sperling & Ann Steffora Mutschler One of the biggest impediments to progress in semiconductor design is progress itself—version after version of specifications, formats and increasingly IP. In fact, there are so many different versions, some of which conflict directly with each other, that it may take months or even years before some customers adopt new products. Much has ... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: IP subsystems

Why IP Subsystems And Why Now?

IP Subsystems: What Works, What Doesn’t

The Integrated IP Subsystem: A Converging SoC Solution

Experts At The Table: Next-Generation IP Landscape

Experts At The Table: Next-Generation IP Landscape

Pitfalls In Subsystem Reuse

Version Control