tag: IP

How IP Subsystems For Chiplets Will Unlock Your Next Wave Of Innovation
By Robert Kruger - 26 Feb, 2026 - Comments: 0

After many years of hope, promises, and commercial challenges, a robust environment that supports multi-die design is now taking shape. These events represent a sea of change for semiconductor design and manufacturing when compared to the traditional single-die monolithic design approach. Moore’s Law drove these original and substantial monolithic design accomplishments. But the massive requi... » read more

Power Leadership At 2nm: Foundation IP Optimized For Next-Gen Hyperscale SoCs
By Andrew Appleby - 12 Feb, 2026 - Comments: 0

By Andrew Appleby and Daryl Seitzer As demand for data center compute accelerates, power efficiency has become the defining metric for modern CPUs, GPUs, and AI accelerators. Every watt saved directly impacts the massive operating costs of gigawatt-scale AI data centers, where power and cooling account for 40–60% of operational expenditures. To reduce energy consumption and strengthen t... » read more

Heterogeneous Multicore System IP
By Nayan Gaywala - 29 Jan, 2026 - Comments: 0

For many of today’s embedded applications, compute requirements demand multiple cores (compute units). These applications also run various types of workloads. A heterogeneous multicore system enables designers to reduce energy and area costs while meeting performance requirements across various workloads. Data crunching by these multiple cores also puts a huge demand on the interconnect and m... » read more

Exploring The Latest Innovations In MIPI D-PHY And MIPI C-PHY
By Michael Nagib - 15 Jan, 2026 - Comments: 0

By Michael Nagib and Nuno Martins In the ever-evolving landscape of high-performance camera and display technologies, MIPI D-PHY and MIPI C-PHY specifications continue to lead the charge, setting benchmarks for low power, low latency, and high bandwidth data transmission. Building on the insights from our previous article, “Demystifying MIPI C-PHY/D–PHY Subsystem” – we now delve into... » read more

Chiplets Vs. Soft IP: Different In Almost Every Way
By Bryon Moyer - 11 Dec, 2025 - Comments: 2

Chiplets serve a similar function as the soft IP widely used in chips today, but the similarities end there. While both can speed time to market and enable design teams to focus limited resources where they can best be applied, the implementation, manufacturing, test, and long-term business requirements wrought by a chiplet marketplace would be very different. Soft IP (also known as RTL IP) ... » read more

Securing IP Integrity In Advanced SoC Design
By Sara Khalaf - 25 Nov, 2025 - Comments: 0

In today’s complex system-on-chip (SoC) design flows, intellectual property (IP) blocks are everywhere—licensed from third parties, leveraged from internal libraries, or hand-crafted by expert teams. These IPs are typically delivered in a “black box” format and are expected to remain unchanged throughout the physical design stages, from initial floorplanning to top-level placement, rout... » read more

A Golden Source As The Single Source Of Truth In HSI
By Tim Schneider - 25 Nov, 2025 - Comments: 0

The hardware/software interface (HSI) is where system-on-chip (SoC) software defines the connections between the software and the underlying hardware. Maintaining a precise, synchronized HSI across all artifacts is challenging, and unmanaged deviations can propagate through the flow and affect integration schedules. Most complex SoCs rely on IP reuse, each with its own naming conventions, ha... » read more

Guarantee IP Integrity With Calibre IP Checker
By Siemens EDA - 25 Nov, 2025 - Comments: 0

In complex SoC designs, intellectual property (IP) blocks are critical yet vulnerable. Unintended modifications to IP during placement, routing or fill stages often go undetected by traditional DRC, leading to functional failures, performance degradation and costly re-spins. This paper introduces Calibre IP Checker, an automated, shift-left solution designed to guarantee IP integrity. It works ... » read more

Silicon IP Continues Steady Growth Path
By Ann Mutschler - 06 Oct, 2025 - Comments: 0

EDA and silicon IP revenue increased 8.6% to $5.089 billion in Q2 2025, up from $4.6855 billion in Q2 2024, according to the ESD Alliance. Total EDA revenue growth was assisted by impressive results in the CAE category, the largest tool sector, which showed 17.2% growth over Q2 2024. “It was another good quarter overall," said Walden C. Rhines, executive sponsor of the SEMI Electronic Desi... » read more

What Does Semiconductor Disruption Look Like?
By Brian Bailey - 25 Sep, 2025 - Comments: 2

When conducting interviews for my article on the incorporation of AI within EDA tools, Anand Thiruvengadam, senior director and head of AI product management at Synopsys, said, "AI has the potential to transform how customers do chip design. The entire EDA flow can be disrupted with AI." He is not alone in making this kind of statement. Each year, I do a predictions piece, and I ask about how A... » read more

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