tag: IP

Executive Insight: Grant Pierce
By Ed Sperling - 27 Jul, 2015 - Comments: 0

Grant Pierce, president and CEO of Sonics, sat down with Semiconductor Engineering to talk about the effects of industry consolidation, China's impact, and the unfolding security threat with the IoT. What follows are excerpts of that interview. SE: Consolidation is one of the big stories right now. What does that mean for your company and the industry as a whole? Pierce: It's a very inter... » read more

Cloud 2.0
By Ed Sperling - 09 Jul, 2015 - Comments: 0

Corporate data centers are reluctant adopters of new technology. There is too much at stake to make quick changes, which accounts for a number of failed semiconductor startups over the past decade with better ideas for more efficient processors, not to mention rapid consolidation in other areas. But as the amount of data increases, and the cost of processing that data decreases at a slower rate... » read more

SoC Connectivity Verification Nightmare
By Kiran Vittal - 09 Jul, 2015 - Comments: 0

At the recent 2015 women’s World Cup soccer final in Canada, Japan was completely caught off guard in the first 15 minutes (and 4 seconds) by the USA. They were wary of the “set-piece” play by the USA team, which they were not able to defend against, resulting in the first three goals by the American women. However, the game breaker was the 54-foot midfield hat-trick goal from Carli Lloyd... » read more

IP Integration Challenges Increase
By Ed Sperling - 08 Jul, 2015 - Comments: 0

Semiconductor Engineering sat down with Chris Rowen, CTO of [getentity id="22032" e_name="Cadence"]'s IP group; Rob Aitken, an [getentity id="22186" comment="ARM"] fellow; Patrick Soheili, vice president of product management and corporate development at [getentity id="22242" e_name="eSilicon"]; Navraj Nandra, senior director of marketing for DesignWare analog and mixed-signal IP at [getentity ... » read more

PCI Express 4.0 Controller Design And Integration Challenges
By Synopsys - 08 Jul, 2015 - Comments: 0

Designers need to start planning for PCI Express 4.0 integration now, because decisions for the PCIe 4.0 controller can have far-reaching consequences for the entire SoC. This paper describes the market adoption and expected use of PCIe 4.0; covers the specification; and discusses three challenges the new specification brings to controller designers. Outline Markets & Applications fo... » read more

EDA Sales Strong Again
By Ed Sperling - 07 Jul, 2015 - Comments: 0

EDA and IP sales were robust again in Q1, up 7.5% to $1.877 billion compared with $1.746 billion in the same period in 2014, according to the EDA Consortium. On the upside, IP revenue rose 19.3% to $618.1 million; services revenue increased 6.8% to $104.4 million; and PCB and multi-chip module revenue increased 1.1% to $161.5 million. On the downside, CAE—the largest single category—... » read more

EDA’s Clouded Future
By Brian Bailey - 25 Jun, 2015 - Comments: 0

There was a time, not that long ago, when chip design and EDA tools consumed some of the largest data centers with tens of thousands of machines and single datasets that consumed more than a hard disk could hold. The existing IT capabilities of the times were stretched to their limits. But while design sizes grew, other aspects of the flow did not develop as fast. “This has been driven by ... » read more

IP Integration Challenges Increase
By Ed Sperling - 24 Jun, 2015 - Comments: 0

Semiconductor Engineering sat down with Chris Rowen, CTO of [getentity id="22032" e_name="Cadence"]'s IP group; Rob Aitken, an [getentity id="22186" comment="ARM"] fellow; Patrick Soheili, vice president of product management and corporate development at [getentity id="22242" e_name="eSilicon"]; Navraj Nandra, senior director of marketing for DesignWare analog and mixed-signal IP at [getentity ... » read more

Managing Dynamic Power
By Ann Mutschler - 16 Jun, 2015 - Comments: 0

Working with finFETs is a study in contrasts. While leakage is now under control for the first time in several process generations due to the advent of different gate technology, dynamic power density caused by tightly packed transistors and higher clock speeds has become the big issue. “FinFET technology helps with reducing static/leakage power so when your logic is not active, you can sh... » read more

SoC Integration Headaches Grow
By Ed Sperling - 16 Jun, 2015 - Comments: 0

As the number of IP blocks grows, so do the headaches of integrating the various pieces and making sure they perform as planned within a prescribed power envelope. This is easier said than done, particularly at the most advanced process nodes. There are more blocks, more power domains, more states and use-model dependencies, and there is much more contention for memories. There are physical ... » read more

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