tag: IP

The Week In Review: Design
By Ed Sperling - 19 Sep, 2014 - Comments: 0

Tools Open-Silicon uncorked a 28Gbps SerDes evaluation platform, complete with board, test chip and characterization data, which it says will speed up and simplify development of chips for 100G networks. The chip utilizes PHY IP from Semtech. IP Synopsys rolled out MIPI C-PHY verification IP that utilizes a three-phase coding technique for faster camera, display and SoC interfaces. http://... » read more

Changing The IP Supplier Paradigm
By Brian Bailey - 17 Sep, 2014 - Comments: 0

Semiconductor Engineering sat down with Rich Wawrzyniak, senior market analyst for ASIC and SoC at Semico Research; John Koeter, vice president of marketing for the Solutions Group at [getentity id="22035" e_name="Synopsys"]; Mike Gianfagna, vice president of marketing for [getentity id="22242" e_name="eSilicon"]; Peter McGuinness, director of technology marketing at [getentity id="22709" e_nam... » read more

More Than Moore
By Ed Sperling - 15 Sep, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the value of feature shrinks and what comes next with Steve Eplett, design technology and automation manager at [getentity id="22664" e_name="Open-Silicon"]; Patrick Soheili, vice president and general manager of IP Solutions at [getentity id="22242" e_name="eSilicon"]; Brandon Wang, engineering group director at [getentity id="22032" e_name="Cadenc... » read more

How Reliable Is Your IP?
By Ed Sperling - 12 Sep, 2014 - Comments: 0

Almost everyone who has bought a new smartphone, car, home electronics device or appliance either has experienced technical glitches that require a replacement or repair, or they know someone who has experienced these problems. The good news is that only a very small fraction of the electronic glitches or failures can be contributed to hardware design. Most of it is due to manufacturing vari... » read more

Advances In Power Management For Physical IP In 28nm And FinFET Process Nodes
By Navraj Nandra - 11 Sep, 2014 - Comments: 0

Engineering techniques to reduce power consumption by lowering the supply voltage and slowing the clock speed have reached practical limits of the semiconductor technologies. Newer solutions, which not only reduce power but also actively manage the power during the course of the SoC (system on chip) activity, are emerging. This article describes these innovations from the foundation intellectua... » read more

Supply Chain Corruption
By Ernest Worthman - 04 Sep, 2014 - Comments: 0

The more the chip supply chain relies on third-party sources, the greater the risk for a design containing potential malicious code or functions. Today, complex and sophisticated ICs are ubiquitous in virtually every industry. They are being relied upon, as never before, to control critical infrastructure subsystems such as power, finance, communications, and transportation. In a recent r... » read more

Changing The IP Supplier Paradigm: Part 2
By Brian Bailey - 26 Aug, 2014 - Comments: 2

Semiconductor Engineering sat down with Rich Wawrzyniak, senior market analyst for ASIC and SoC at Semico Research; John Koeter, vice president of marketing for the Solutions Group at [getentity id="22035" e_name="Synopsys"]; Mike Gianfagna, vice president of marketing for [getentity id="22242" e_name="eSilicon"]; Peter McGuinness, director of technology marketing at [getentity id="22709" e_nam... » read more

Not Invented Here Syndrome
By Jon McDonald - 21 Aug, 2014 - Comments: 0

Recently I have made some choices on IP I needed to re-use and some I decided not to re-use. This got me thinking about the general topic of reuse in system-level design. Most will agree with a non-specific statement that reuse is a good thing, but the details tend to be a bit more ambiguous. Clouding the reuse question are occasional infections of NIH Syndrome (Not Invented Here), even if s... » read more

More Than Moore
By Ed Sperling - 21 Aug, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the value of feature shrinks and what comes next with Steve Eplett, design technology and automation manager at Open-Silicon; Patrick Soheili, vice president and general manager of IP Solutions at eSilicon; Brandon Wang, engineering group director at Cadence; John Ferguson, product manager for DRC applications at Mentor Graphics; and Kevin Kranen, d... » read more

Executive Insight: Jack Harding
By Ed Sperling - 18 Aug, 2014 - Comments: 0

SE: What’s worrying you these days? Harding: One thing that bothers me is the cost of chip development on a per-chip basis. We seduce ourselves into thinking everything is wonderful because the cost per transistor is dropping in chunks. Gate costs are going down at every node. If you look at the secular trend, we’ve done a pretty good job putting a lot of stuff in a small space. In my bu... » read more

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