tag: IR drop

Voltage Drop Now Requires Dynamic Analysis
By Karen Heyman - 08 Aug, 2024 - Comments: 0

At one time a relatively infrequent occurrence, voltage drop is now a major impediment to reliability at advanced nodes. Decades ago, voltage drop was only an issue for very large and high-speed designs, where there was concern about supply lines delivering full voltage to transistors. As design margins have tightened in modern advanced designs, controlling voltage drop has become a requiremen... » read more

A Hybrid ECO Detailed Placement Flow for Mitigating Dynamic IR Drop (UC San Diego)
By Technical Paper Link - 01 Aug, 2024 - Comments: 0

A new technical paper titled "A Hybrid ECO Detailed Placement Flow for Improved Reduction of Dynamic IR Drop" was published by researchers at UC San Diego. Abstract: "With advanced semiconductor technology progressing well into sub-7nm scale, voltage drop has become an increasingly challenging issue. As a result, there has been extensive research focused on predicting and mitigating dynam... » read more

ML Method To Predict IR Drop Levels
By Technical Paper Link - 21 Jun, 2024 - Comments: 0

A new technical paper titled "IR drop Prediction Based on Machine Learning and Pattern Reduction" was published by researchers at National Tsing Hua University, National Taiwan University of Science and Technology, and MediaTek. Abstract (partial) "In this paper, we propose a machine learning-based method to predict IR drop levels and present an algorithm for reducing simulation patterns, w... » read more

Integrated, Turnkey Droop Response System: Heterogeneous IP Use Case
By Movellus - 29 May, 2024 - Comments: 0

Whether you serve the ADAS, PC, or networking market, chances are that your SoC is heterogeneous; containing general processors and application-specific accelerators. Your solution might have a systolic array for convolutions, a cluster of CPUs for application code, or a look-aside crypto engine for packet security. While application-specific accelerators significantly improve performance and p... » read more

Electromigration And IR Drop At Advanced Nodes
By Ed Sperling - 22 May, 2024 - Comments: 0

Manufacturing chips at 3nm and below is a challenge, but it's only part of the problem. Designing chips that can be manufactured and will actually work is potentially an even bigger problem. There is more data to sift through for place-and-route, less margin to pad a design, and there are more physical effects to contend with as transistors get taller, density increases, and chips age. Jeff Wil... » read more

Using AI/ML To Minimize IR Drop
By Ann Mutschler - 11 Apr, 2024 - Comments: 1

IR drop is becoming a much bigger problem as technology nodes scale and more components are packed into advanced packages. This is partly a result of physics, but it's also the result of how the design flow is structured. In most cases, AI/ML can help. The underlying problem is that moving to advanced process nodes, and now 3D-ICs, is driving current densities higher, while the power envelop... » read more

Power Sub-Mesh Construction To Mitigate IR Drop And Minimize Routing Overhead (Intel)
By Technical Paper Link - 02 Apr, 2024 - Comments: 0

A new technical paper titled "Power Sub-Mesh Construction in Multiple Power Domain Design with IR Drop and Routability Optimization" was published by researchers at Intel Corporation and National Taiwan University. Abstract: "Multiple power domain design is prevalent for achieving aggressive power savings. In such design, power delivery to cross-domain cells poses a tough challenge at adv... » read more

Which Data Works Best For Voltage Droop Simulation
By Ann Mutschler - 15 Jan, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk about the need for the right type of data, why this has to be done early in the design flow, and how 3D-IC will affect all of this, with Bill Mullen, distinguished engineer at Ansys; Rajat Chaudhry, product management group director at Cadence; Heidi Barnes, senior applications engineer at Keysight; Venkatesh Santhanagopalan, prod... » read more

Analog Design Complicates Voltage Droop
By Ann Mutschler - 27 Dec, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk about voltage droop in analog and mixed-signal designs, and the need for multi-vendor tool interoperability and more precision, with Bill Mullen, distinguished engineer at Ansys; Rajat Chaudhry, product management group director at Cadence; Heidi Barnes, senior applications engineer at Keysight; Venkatesh Santhanagopalan, product ... » read more

Managing P/P Tradeoffs With Voltage Droop Gets Trickier
By Ann Mutschler - 14 Sep, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk about voltage droop/IR drop with Bill Mullen, distinguished engineer at Ansys; Rajat Chaudhry, product management group director at Cadence; Heidi Barnes, senior applications engineer at Keysight Technologies; Venkatesh Santhanagopalan, product manager at Movellus; Joe Davis, senior director for Calibre interfaces and mPower EM/IR... » read more

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