tag: JCET

Bridges Vs. Interposers
By Mark LaPedus - 12 Jul, 2018 - Comments: 4

The number of technology options continue to grow for advanced packaging, including new and different ways to incorporate so-called silicon bridges in products. For some time, Intel has offered a silicon bridge technology called Embedded Multi-die Interconnect Bridge (EMIB), which makes use of a tiny piece of silicon with routing layers that connects one chip to another in an IC package. In ... » read more

OSAT Consolidation Continues
By Jeff Dorsch - 14 May, 2018 - Comments: 0

Advanced Semiconductor Engineering (ASE) and Siliconware Precision Industries Ltd. (SPIL) are beginning the process of uniting the two companies, which are among the largest outsourced semiconductor assembly and testing contractors in the world. For now, the companies will continue to operate separately, while their shares are traded under the ASX symbol on the New York Stock Exchange. ASE I... » read more

MIS Packaging Takes Off
By Mark LaPedus - 07 May, 2018 - Comments: 0

Momentum is building for IC packages based on an emerging technology called molded interconnect substrate (MIS). ASE, Carsem, JCET/STATS ChipPAC, Unisem and others are developing IC packages based on MIS substrate technology, which is ramping up in the analog, power IC and even the cryptocurrency markets. MIS starts with a specialized substrate material for select IC packages. The MIS sub... » read more

Packaging Chips For Cars
By Jeff Dorsch - 07 May, 2018 - Comments: 2

As the complexity of automotive chips grows, so does the complexity of the package. In fact, packaging is becoming increasingly crucial to the performance and reliability of the chips, and both parts need to meet stringent safety standards before they are used inside a vehicle. This is true for all safety-critical applications, but for automotive in particular there are several key reasons w... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 04 May, 2018 - Comments: 0

Chipmakers Consumers recently filed a class-action suit against the three DRAM makers, alleging that they illegally agreed to raise prices for their respective memory products. The suit, filed in the U.S. District Court for the Northern District of California, alleges that Samsung, Micron and Hynix agreed to limit the supply of DRAM, driving up prices for this widely used memory. The pri... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 20 Apr, 2018 - Comments: 2

Trade The trade tensions are building between the U.S. and China. In the latest move, the U.S. Department of Commerce has imposed a ban on U.S. companies selling chips to ZTE, a Chinese telecom equipment and mobile phone vendor. The ban has been implemented on ZTE for seven years after the firm “was caught illegally shipping U.S. goods to Iran,” according to a report from Reuters. This ... » read more

Innovative Integration Solutions For SiP Packages Using Fan-Out Wafer Level eWLB Technology
By STATS ChipPAC - 05 Mar, 2018 - Comments: 0

Fan-Out Wafer Level Packaging (FOWLP) has been established as one of the most versatile packaging technologies in the recent past and already accounts for a market value of over 1 billion USD due to its unique advantages. The technology combines high performance, increased functionality with a high potential for heterogeneous integration and reduced overall form factor as well as cost effective... » read more

Fan-Out Wars Begin
By Mark LaPedus - 05 Feb, 2018 - Comments: 3

Several packaging houses are developing the next wave of high-density fan-out packages for premium smartphones, but perhaps a bigger battle is brewing in the lower density fan-out arena. Amkor, ASE, STATS ChipPAC and others sell traditional low-density fan-out packages, although some new and competitive technologies are beginning to appear in the market. Low-density fan-out, or sometimes cal... » read more

Cheaper Packaging Options Ahead
By Ed Sperling - 05 Feb, 2018 - Comments: 0

Lower-cost packaging options and interconnects are either under development or just being commercialized, all of which could have a significant impact on the economics of advanced packaging. By far, the most cited reason why companies don't adopt advanced [getkc id="27" kc_name="packaging"] is cost. Currently, silicon [getkc id="204" kc_name="interposers"] add about $30 to the price of a med... » read more

Fan-Out Wafer Level eWLB Technology As An Advanced System-in-Package Solution
By STATS ChipPAC - 05 Feb, 2018 - Comments: 0

System-in-Package (SiP) technology continues to be essential for higher integration of functional blocks to meet the ever demanding market needs with respect to smaller form factor, lower cost and time to market. A typical SiP incorporates all or some form of Fan-Out Wafer Level packaging, wire bonding or flip chip that serves a multitude of applications such as optoelectronics, RF, power ampli... » read more

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