Chip Industry Week in Review


AI featured big at this week's Design Automation Conference (DAC) in San Francisco. Dozens of companies featured AI-related tools (see product section below), as well as significant improvements to existing tools and some entirely new approaches for designing chips. Among the highlights: Siemens unveiled an AI-enhanced toolset for the EDA design flow that enables customers to integrate the... » read more

Chip Industry Week in Review


Texas Instruments will invest more than $60 billion to build and expand seven semiconductor fabs in Texas and Utah, supporting more than 60,000 U.S. jobs. Chinese automakers — including SAIC Motor, Changan, Great Wall Motor, BYD, Li Auto and Geely — are aiming to launch new models with 100% homemade chips, some as early as 2026, reports Nikkei Asia. Marvell introduced 2nm custom SRAM ... » read more

Chip Industry Technical Paper Roundup: June 17


New technical papers recently added to Semiconductor Engineering’s library: [table id=440 /] Find more semiconductor research papers here.   » read more

HBM Roadmap: Next-Gen High-Bandwidth Memory Architectures (KAIST’s TERALAB)


A new technical paper titled "HBM Roadmap Ver 1.7 Workshop" was published by researchers at KAIST’s TERALAB. The 371-page paper provides an overview of next-generation HBM architectures based on current technology trends, as well as many technology insights. Find the technical paper here or here.  Published June 2025. Advising Professor : Prof. Joungho Kim. Fig. 1: Thermal Manag... » read more

Chip Industry Week in Review


The Chinese Academy of Sciences unveiled a fully automated processor chip design system, claiming the potential to accelerate semiconductor development and replace human programmers. Micron Technology plans to expand its U.S. investments to approximately $150 billion in domestic memory manufacturing and $50 billion in R&D, which is $30 billion higher than previously reported. AMD laun... » read more

Chip Industry Technical Paper Roundup: June 3


New technical papers recently added to Semiconductor Engineering’s library: [table id=436 /] Find more semiconductor research papers here. » read more

Offline RL Framework That Dynamically Controls The GPU Clock And Server Fan Speed To Optimize Power Consumption And Computation Time (KAIST)


A new technical paper titled "Power Consumption Optimization of GPU Server With Offline Reinforcement Learning" was published by researchers at Korea Advanced Institute of Science and Technology (KAIST) and KT Research and Development Center. "Optimizing GPU server power consumption is complex due to the interdependence of various components. Conventional methods often involve trade-offs: in... » read more

Chip Industry Technical Paper Roundup: Apr. 29


New technical papers recently added to Semiconductor Engineering’s library: [table id=424 /] Find more semiconductor research papers here. » read more

Challenges of Chiplet Placement And Routing Optimization (KAIST)


A new technical paper titled "Advanced Chiplet Placement and Routing Optimization considering Signal Integrity" was published by researchers at KAIST. Abstract: "This article addresses the critical challenges of chiplet placement and routing optimization in the era of advanced packaging and heterogeneous integration. We present a novel approach that formulates the problem as a signal integr... » read more

HW-based Heterogeneous Memory Management for LLM Inferencing (KAIST, Stanford Unversity)


A new technical paper titled "Hardware-based Heterogeneous Memory Management for Large Language Model Inference" was published by researchers at KAIST and Stanford University. Abstract "A large language model (LLM) is one of the most important emerging machine learning applications nowadays. However, due to its huge model size and runtime increase of the memory footprint, LLM inferences suf... » read more

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