Chip Industry Technical Paper Roundup: Apr. 29


New technical papers recently added to Semiconductor Engineering’s library: [table id=424 /] Find more semiconductor research papers here. » read more

Challenges of Chiplet Placement And Routing Optimization (KAIST)


A new technical paper titled "Advanced Chiplet Placement and Routing Optimization considering Signal Integrity" was published by researchers at KAIST. Abstract: "This article addresses the critical challenges of chiplet placement and routing optimization in the era of advanced packaging and heterogeneous integration. We present a novel approach that formulates the problem as a signal integr... » read more

HW-based Heterogeneous Memory Management for LLM Inferencing (KAIST, Stanford Unversity)


A new technical paper titled "Hardware-based Heterogeneous Memory Management for Large Language Model Inference" was published by researchers at KAIST and Stanford University. Abstract "A large language model (LLM) is one of the most important emerging machine learning applications nowadays. However, due to its huge model size and runtime increase of the memory footprint, LLM inferences suf... » read more

Research Bits: Apr. 15


Shape-morphing OLED panel with built-in speaker Researchers from Pohang University of Science and Technology (POSTECH) developed a flexible OLED panel that can freely transform its shape while simultaneously functioning as a speaker. The design is based on a based on a specialized ultra-thin piezoelectric polymer actuator that when integrated into a flexible OLED panel enables electrically ... » read more

Chip Industry Technical Paper Roundup: Feb. 18


New technical papers recently added to Semiconductor Engineering’s library: [table id=406 /] Find all technical papers here. » read more

Chip Industry Week In Review


Worldwide silicon wafer shipments declined nearly 2.7% to 12,266 million square inches in 2024, with wafer revenue contracting 6.5% to $11.5 billion, according to the SEMI Silicon Manufacturers Group. CSIS released a new report, “Critical Minerals and the Future of the U.S. Economy,” with detailed analysis and policy recommendations for building a secure mineral supply chain for semicond... » read more

Rowhammer Mitigation With Adaptive Refresh Management Optimization (KAIST, Sk hynix)


A new technical paper titled "Securing DRAM at Scale: ARFM-Driven Row Hammer Defense with Unveiling the Threat of Short tRC Patterns" was published by researchers at KAIST and Sk hynix. Abstract (partial) "To address the issue of powerful row hammer (RH) attacks, our study involved an extensive analysis of the prevalent attack patterns in the field. We discovered a strong correlation betwee... » read more

Med Tech Morphs Into Consumer Wearables


Doctors have been using advanced technology for years, but the growing trend is for consumers to use devices at home and have direct access to their data. Watches and rings that were once primarily used for counting steps or registering sleep patterns can now read blood pressure, heart rate, blood oxygen, body temperature, and other early signs of illness. Meanwhile, various patches are under d... » read more

Research Bits: Jan. 20


Self-correcting memristor array Researchers at Korea Advanced Institute of Science and Technology (KAIST), Seoul National University, Sungkyunkwan University, Electronics and Telecommunications Research Institute (ETRI), and Yonsei University developed a memristor-based neuromorphic chip that can learn and correct errors, enabling it to adapt to immediate environmental changes. The system c... » read more

Chip Industry Week in Review


Lawrence Livermore National Laboratory is ramping up R&D for next-gen EUV and plasma-based particle sources, aiming to increase the EUV laser source power by an order of magnitude while also making it more energy-efficient. Specifically, the goal is to replace today's CO2-based laser with a solid-state laser, using a thulium-doped yttrium lithium fluoride medium to increase the laser's powe... » read more

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