Week In Review: Design, Low Power

By Marie C. Baca - 02 Dec, 2022 - Comments: 0

Tools and IP Renesas released a family of configurable clock generators with an internal crystal oscillator for PCIe and networking applications in high-end computing, wired infrastructure and data center equipment. “Timing needs can vary greatly between different applications and equipment, and often change during a product design cycle,” said Zaher Baidas, Vice President of the Timing Pr... » read more

Improving Concurrent Chip Design, Manufacturing, And Test Flows

By Ann Mutschler - 28 Nov, 2022 - Comments: 0

Semiconductor design, manufacturing, and test are becoming much more tightly integrated as the chip industry seeks to optimize designs using fewer engineers, setting the stage for greater efficiencies and potentially lower chip costs without just relying on economies of scale. The glue between these various processes is data, and the chip industry is working to weave together various steps t... » read more

6 Oscilloscope Tricks To Get The Most Out Of Your Scope

By Keysight - 23 Nov, 2022 - Comments: 0

Get the most out of your oscilloscope with these six tips covering basic triggering, probing, scaling signals, using the right acquisition mode, and more. Click here to read more. » read more

EDA Tools For Quantum Chips

By Marie C. Baca - 22 Nov, 2022 - Comments: 0

Commercially viable quantum computers are at least several years away, but some researchers already are questioning whether existing EDA tools will be sufficient for designing quantum chips and systems. That’s because quantum design requirements at times transcend classical rules about materials, temperature, and structure — rules that are foundational for the majority of EDA products on th... » read more

Week In Review: Design, Low Power

By Marie C. Baca - 18 Nov, 2022 - Comments: 0

Tools and IP Cadence announced that its IP for GDDR6 is now silicon-proven for TSMC’s N5 process technology. The IP consists of Cadence PHY, controller design IP, and verification IP (VIP), and is targeted for very high-bandwidth memory applications. “The improved PHY and controller design IP for GDDR6 with DRAM data rates at 22Gbps in the TSMC N5 process is the fastest of the GDDR6 fami... » read more

Managing IP In Heterogeneous Designs

By Ed Sperling - 14 Nov, 2022 - Comments: 0

Increasing complexity and heterogeneity is creating huge challenges for tracking different versions of IP over the lifetime of chips. Pedro Pires, applications engineer at ClioSoft, talks about the implications of IP reuse in a complex, multi-IP context, including how different standards and database formats can affect IP tracking and why an interoperability layer is essential to tracking IP an... » read more

Week In Review: Design, Low Power

By Jesse Allen - 11 Nov, 2022 - Comments: 0

Chip design Fraunhofer IIS/EAS implemented the Bunch of Wires (BoW) standard-based interface IP from the Open Compute Project (OCP) on Samsung's 5nm technology. The effort is intended to make chiplets more feasible for products with small and medium-sized production runs and determine the need for additional uniform standards in the future, such as for die-to-die bonding. “As part of t... » read more

Week In Review: Design, Low Power

By Marie C. Baca - 04 Nov, 2022 - Comments: 0

Earnings and Acquisitions Siemens will acquire Avery Design Systems, a simulation-independent verification IP supplier, in the first quarter of fiscal year 2023. The terms of the transaction were not disclosed. Siemens executives say the acquisition will “enhance Siemens’ offerings across mainstream verification IP segments, while further extending Siemens verification solutions into area... » read more

Post-Quantum And Pre-Quantum Security Issues Grow

By Marie C. Baca - 03 Nov, 2022 - Comments: 2

General-purpose quantum computers will be able to crack the codes that protect much of the world’s information, and while these machines don’t exist yet, security experts say governments and businesses are starting to prepare for encryption in a post-quantum world. The task is made all the more challenging because no one knows exactly how future quantum machines will work, or even which mat... » read more

Chip Design Shifts As Fundamental Laws Run Out Of Steam

By Ann Mutschler - 31 Oct, 2022 - Comments: 12

Dennard scaling is gone, Amdahl's Law is reaching its limit, and Moore's Law is becoming difficult and expensive to follow, particularly as power and performance benefits diminish. And while none of that has reduced opportunities for much faster, lower-power chips, it has significantly shifted the dynamics for their design and manufacturing. Rather than just different process nodes and half ... » read more

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Knowledge Centers
Entities, people and technologies explored

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: Keysight

Week In Review: Design, Low Power

Improving Concurrent Chip Design, Manufacturing, And Test Flows

6 Oscilloscope Tricks To Get The Most Out Of Your Scope

EDA Tools For Quantum Chips

Week In Review: Design, Low Power

Managing IP In Heterogeneous Designs

Week In Review: Design, Low Power

Week In Review: Design, Low Power

Post-Quantum And Pre-Quantum Security Issues Grow

Chip Design Shifts As Fundamental Laws Run Out Of Steam

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