Chip Industry Week in Review


The Biden-Harris Administration announced preliminary terms with HP for $50 million in direct funding under the CHIPs and Science Act to support the expansion and modernization of HP’s existing microfluidics and microelectromechanical systems (“MEMS”) facility in Corvallis, Oregon. CHIPS for America launched the CHIPS Metrology Community, a collaborative initiative designed to advance ... » read more

Energy Efficiency As A Native Network Attribute Through 6G


Energy efficiency offers positive societal benefits in both environmental and economic ways, such as lowering pollutants and utility bills. As such, the global community is looking toward technological advancements to help drive a more sustainable future. One such technology that offers opportunities in this space is 6G. Utilizing its unparalleled speed and connectivity, and powered by the tran... » read more

Edge Devices Require New Security Approaches


The diversity of connected devices and chips at the edge — the vaguely defined middle ground between the end point and the cloud — is significantly widening the potential attack surface and creating more opportunities for cyberattacks. The edge build-out has been underway for at least the past half-decade, largely driven by an explosion in data and increasing demands to process that data... » read more

Developing Workflows To Streamline System-Level Design


Experts At The Table: One of the big challenges facing EDA companies is explaining to customers what's possible, how to streamline their designs, and what can be accomplished at what level of risk. Semiconductor Engineering sat down to talk about how relationships are fundamentally changing between EDA companies and their customers Michal Siwinski, chief marketing officer at Arteris; Chris Muet... » read more

Blog Review: Aug. 28


Synopsys' Jon Ames checks out how the Ultra Ethernet Consortium aims to revolutionize networking by optimizing Ethernet for the rapidly evolving AI and HPC workloads by addressing critical issues like tail latency that are encountered by machine learning algorithms in large compute clusters. Cadence's Kos Gitchev introduces the DDR5 Multiplexed Rank DIMM (MRDIMM), a memory module technology ... » read more

Wire Bond Electrical Structural Test Methodologies


Wire bonding, a foundational process in microelectronics, is essential to establishing a robust and low-resistance electrical connection between semiconductor chips and their respective packages or, in the case of multi-chip modules, between different chips. This intricate process ensures the device's functionality, reliability, and overall performance. Wire bonding faces several challenges ... » read more

Hardware Security Set To Grow Quickly


Experts At The Table: The hardware security ecosystem is young and relatively small but could see a major boom in the coming years. As companies begin to acknowledge how vulnerable their hardware is, industry standards are being set, but must leave room for engineers to experiment. As part of an effort to determine the best way forward, Semiconductor Engineering sat down with a panel of experts... » read more

Blog Review: Aug. 21


Cadence's Reela Samuel explores the critical role of PCIe 6.0 equalization in maintaining signal integrity and solutions to mitigate verification challenges, such as creating checkers to verify all symbols of TS0, ensuring the correct functioning of scrambling, and monitoring phase and LTSSM state transitions. Siemens' John McMillan introduces an advanced packaging flow for Intel's Embedded ... » read more

Chip Industry Week In Review


The U.S. Department of Commerce and Texas Instruments (TI) signed a non-binding preliminary memorandum of terms to provide up to $1.6 billion in CHIPS Act funding towards TI’s investment of over $18 billion for three 300mm semiconductor wafer fabs under construction in Texas and Utah. TI also expects to get about $6 billion to $8 billion from the U.S. Department of Treasury’s Investmen... » read more

Blog Review: Aug. 14


Cadence's Dimitry Pavlovsky highlights two new features in the AMBA CHI protocol Issue G update that enhance security of the Arm architecture: Memory Encryption Contexts, which allows data in each Realm in the memory to be encrypted with a different encryption key, and Device Assignment, which introduces hardware provisions to support fully coherent caches in partially trusted remote coherent d... » read more

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