tag: Keysight

Week In Review: IoT, Security, Autos
By SE Staff - 24 Jan, 2020 - Comments: 0

AI/Edge Vastai Technologies is using Arteris IP’s FlexNoC Interconnect IP and AI Package for its Artificial Intelligence Chips for artificial intelligence and computer vision systems-on-chip (SoCs). Startup Vastai Technologies was founded in December 2018, designs ASICs and software platforms for computer vision and AI applications, such as smart city, smart surveillance, smart education, ac... » read more

Network Storage Optimization In Chip Design
By Ed Sperling - 21 Jan, 2020 - Comments: 0

Prathna Sekar, technical account manager at ClioSoft, explains how to manage large quantities of data, how this can quickly spin out of control as colleagues check in data during the design process, and how to reduce the amount that needs to be stored. » read more

Moore’s Law, Supply Chains And Security
By Brian Bailey - 16 Jan, 2020 - Comments: 0

The debate about the future of Moore's Law continues, while other parts of the industry look for alternatives. In between, supply chains are being pulled in multiple directions, with safety and security often in the middle. All across the semiconductor industry, significant changes are underway. Some of these have been in the works for some time. Others are new or accelerating faster than an... » read more

Big Growth Areas: Connectivity, AI, Reliability
By Brian Bailey - 14 Jan, 2020 - Comments: 0

Connectivity and artificial intelligence (AI) will be the biggest drivers for 2020, with an emphasis on improved reliability across all areas. New standards, new applications, and new pressures being placed on old technology will created boundless opportunities for those ready to fill the need. Of course, there will also be a lot of carnage along the way, and we can expect to see a lot of that ... » read more

Auto Industry Shifts Gears On Where Data Gets Processed
By Ann Mutschler - 09 Jan, 2020 - Comments: 0

In-vehicle processing is becoming a major challenge in automotive electronics due to the massive amount of data being generated by sensors — especially cameras — and the rapid response time required to avoid accidents. The initial idea that all data could be sent to the cloud for processing has been shelved, most likely permanently. In its place is a growing recognition that data needs t... » read more

Can You Afford To Waste Time On Your Next Design Project?
By Amit Varde - 09 Jan, 2020 - Comments: 0

Let’s be honest: engineers are asked to perform miracles every day, and they almost always deliver. They are challenged to invent the future in the form of newly sophisticated, powerful and highly functional systems-on-chips and systems. On top of this, they’re required to do so with an increasingly complex array of tools and re-use increasing amounts of IP to speed time-to-market. Oh, and ... » read more

Challenges In IP Reuse
By Ed Sperling - 09 Dec, 2019 - Comments: 0

Jeff Markham, software architect at ClioSoft, explains why IP reuse is so important in advanced process node SoC chip designs, what companies need to keep track of when working with third-party IP, and how it needs to be characterized. » read more

Thoroughly Verifying Complex SoCs
By Ann Mutschler - 26 Nov, 2019 - Comments: 0

The number of things that can go wrong in complex SoCs targeted at leading-edge applications is staggering, and there is no indication that verifying these chips will function as expected is going to get any easier. Heterogeneous designs developed for leading-edge applications, such as 5G, IoT, automotive and AI, are now complex systems in their own right. But they also need to work in conju... » read more

Managing Analog Designs For Successful Tapeouts
By Cliosoft - 06 Nov, 2019 - Comments: 0

Managing analog designs beyond data management to IP reuse and beyond in order to create a collaborative platform for design management from concept-to-GDSII. Click here to read more. » read more

IP Management And Development At 5/3nm
By Ann Mutschler - 24 Oct, 2019 - Comments: 1

The growing complexity of moving to new process nodes is making it much more difficult to create, manage and re-use IP. There are more rules, more data to manage, and more potential interactions as density increases, both in planar implementations and in advanced packaging. And the problems only get worse as designs move to 5nm and 3nm, and as more heterogeneous components such as accelerato... » read more

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