Changes In Chip Design

By Ernest Worthman - 07 Jan, 2016 - Comments: 0

We all know that sub-10nm is coming. But is that really what will define the next generation of semiconductors? Progress in semiconductor technology increasingly is not just about advancements in the hardware. It also involves advancements in applications and technologies peripheral to the devices themselves. That may sound counterintuitive, but going forward the technology, applications and... » read more

OTP Dynamic Power Cut By Factor Of 10

By Kilopass - 03 Dec, 2015 - Comments: 0

Of the challenges being addressed by Internet of Things (IoT) designers around the globe, none is more pressing than the need to reduce edge-node power. While eyes often turn to the radio as primary consumer of energy, memory, including NVM memory, also contributes a substantial portion of the energy consumed by an edge node. Power reductions in all memories will be essential for meeting this c... » read more

Low-Power Considerations For IoT Devices

By Charlie Cheng - 03 Dec, 2015 - Comments: 0

The concept of the Internet of Things has produced plenty of fanciful thinking about what’s possible. There are some wonderfully creative idea, not all of them practical. That's too bad, because there are ample areas that could benefit from functional IoT devices, such as: • Infrastructure sensors for buildings and bridges; • Medical sensors for use on or inside the body; • Oil drill... » read more

Memory Choices Grow

By Ed Sperling - 24 Nov, 2015 - Comments: 1

Memory is becoming one of the starting points for SoC architectures, evolving from a basic checklist item that was almost always in the shadow of improving processor performance or lowering the overall power budget. In conjunction with that shift, chipmakers must now grapple with many more front-end decisions about placement, memory type and access prioritization. There are plenty of rules ... » read more

One-Time-Programmable Dynamic Power Cut By Factor Of 10

By Kilopass - 18 Nov, 2015 - Comments: 0

The Week In Review: Design/IoT

By Jesse Allen - 13 Nov, 2015 - Comments: 0

Predictions Wally Rhines, Mentor Graphics' chairman and CEO, was presented with the Kaufman Award last night for outstanding achievement in electronic design. In his acceptance speech, he plotted the growth of the EDA industry at a consistent 2% of the semiconductor industry for the past couple decades. But he noted that with a shift to system design automation, that number would rise from t... » read more

Tech Talk: Lower Power Embedded NVM

By Ed Sperling - 12 Nov, 2015 - Comments: 0

Jen-Tai Hsu, Kilopass' vice president of engineering, talks about lower-voltage bit cells, where they fit in IoT designs and how they affect battery life. [youtube vid=dNDkuApHumU] » read more

Security Improvements Ahead

By Ed Sperling - 10 Nov, 2015 - Comments: 0

After nearly two years of talking about how security is one of the biggest problems facing the IoE, progress is being made on a number of fronts. The changes involve many companies, both individually and collaboratively through standards groups. And while none of this will stop the kind of high-profile breaches that affected Target or Home Depot or JPMorgan Chase or a long list of other gian... » read more

The Great IoE Race Begins

By Ed Sperling - 05 Nov, 2015 - Comments: 0

Nobody knows how many tens of billions of semiconductors will be used in the IoE, but it's a sure bet it won't be a few chips replicated billions of times. Most IoE devices will need to be customized for specific applications. Many will need to be highly reliable for many years. And all of them will need to be secure and power-efficient. Yet they also will need to connect to heterogeneous ne... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

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