tag: KLA

Planning For Panel-Level Fan-out
By Mark LaPedus - 21 Nov, 2019 - Comments: 0

Several companies are developing or ramping up panel-level fan-out packaging as a way to reduce the cost of advanced packaging. Wafer-level fan-out is one of several advanced packaging types where a package can incorporate dies, MEMS and passives in an IC package. This approach has been in production for years, and is produced in a round wafer format in 200mm or 300mm wafer sizes. Fan-out... » read more

Different Ways To Improve Chip Reliability
By Ed Sperling - 12 Nov, 2019 - Comments: 1

A push toward greater reliability in safety- and mission-critical applications is prompting some innovative approaches in semiconductor design, manufacturing, and post-production analysis of chip behavior. While quality over time has come under intensive scrutiny in automotive, where German carmakers require chips to last 18 years with zero defects, it isn't the only market demanding extende... » read more

Test In New Frontiers: Flexible Circuits
By Susan Rambo - 12 Nov, 2019 - Comments: 0

Test is becoming increasingly complicated as new technologies such as flexible electronics begin playing mission-critical roles in applications where electronics have little or no history. Although flexible circuitry has been around for while, testing needs to catch up as these circuits are deployed across a variety of markets where conditions may be extreme. In many cases, sensors for monit... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 01 Nov, 2019 - Comments: 0

Chipmakers China has created a new $29 billion fund to help advance its semiconductor sector, according to reports from Bloomberg and others. Here's another report. The The U.S. and China are in the midst of a trade war. This has prompted China to accelerate its efforts to become more self-sufficient in semiconductor design and production. This includes DRAMs as well as logic/foundry. -----... » read more

Power Semi Wars Begin
By Mark LaPedus - 23 Oct, 2019 - Comments: 1

Several vendors are rolling out the next wave of power semiconductors based on gallium nitride (GaN) and silicon carbide (SiC), setting the stage for a showdown against traditional silicon-based devices in the market. Power semiconductors are specialized transistors that incorporate different and competitive technologies like GaN, SiC and silicon. Power semis operate as a switch in high-volt... » read more

Making Random Variation Less Random
By Ed Sperling - 21 Oct, 2019 - Comments: 0

The economics for random variation are changing, particularly at advanced nodes and in complex packaging schemes. Random variation always will exist in semiconductor manufacturing processes, but much of what is called random has a traceable root cause. The reason it is classified as random is that it is expensive to track down all of the various quirks in a complex manufacturing process or i... » read more

What’s The Best Advanced Packaging Option?
By Mark LaPedus - 17 Oct, 2019 - Comments: 2

As traditional chip designs become more unwieldy and expensive at each node, many IC vendors are exploring or pursuing alternative approaches using advanced packaging. The problem is there are too many advanced packaging options on the table already, and the list continues to grow. Moreover, each option has several tradeoffs and challenges, and all of them are still relatively expensive. ... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 11 Oct, 2019 - Comments: 0

Fab tools A consortium of 31 companies have launched a new project, called the “Advanced packaging for photonics, optics and electronics for low cost manufacturing in Europe.” The program is referred to as APPLAUSE. With a budget of 34 million euros, the project is being coordinated by ICOS, a division of KLA. “APPLAUSE will focus on advanced optics, photonics and electronics packagin... » read more

Reducing Costly Flaws In Heterogeneous Designs
By Ed Sperling - 08 Oct, 2019 - Comments: 0

The cost of defects is rising as chipmakers begin adding multiple chips into a package, or multiple processor cores and memories on the same die. Put simply, one bad wire can spoil an entire system. Two main issues need to be solved to reduce the number of defects. The first is identifying the actual defect, which becomes more difficult as chips grow larger and more complex, and whenever chi... » read more

The Race To Next-Gen 2.5D/3D Packages
By Mark LaPedus - 23 Sep, 2019 - Comments: 4

Several companies are racing each other to develop a new class of 2.5D and 3D packages based on various next-generation interconnect technologies. Intel, TSMC and others are exploring or developing future packages based on one emerging interconnect scheme, called copper-to-copper hybrid bonding. This technology provides a way to stack advanced dies using copper connections at the chip level,... » read more

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