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Week In Review: Manufacturing, Test

Packaging project; 5nm; 3D chips; neural-net-on-a-chip.

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Fab tools
A consortium of 31 companies have launched a new project, called the “Advanced packaging for photonics, optics and electronics for low cost manufacturing in Europe.” The program is referred to as APPLAUSE. With a budget of 34 million euros, the project is being coordinated by ICOS, a division of KLA.

“APPLAUSE will focus on advanced optics, photonics and electronics packaging for multimodal sensing systems. High-volume manufacturing is supported by a strong contribution from process and process control equipment R&D,” said Pieter Vandewalle, general manager of ICOS. Click here for more information about the project.

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Multibeam has a project underway to thwart the counterfeiting of ICs. The project involves the company’s multi-column electron-beam lithography (MEBL) technology. The MEBL system application is funded by an $8.2 million contract awarded by the Air Force Research Laboratory (AFRL) under the Assured and Trusted Microelectronics Solutions (ATMS) program.

Multibeam will expand the capability of its MEBL system, concurrently being built under a separate U.S. Department of Defense contract, to embed an ID into each chip. Multibeam’s system embeds “hard coding” inside each IC during the fabrication process. This makes the ID secure and tamper-proof. “The rampant forging of ICs remains a serious industry problem,” said David Lam, chairman and chief executive of Multibeam. “Our multi-column e-beam lithography (MEBL) technology provides a most effective solution to embed a secure, unique identity (ID) into each IC cost-efficiently.”

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FormFactor has acquired FRT, a supplier of metrology tools. FRT manufactures surface metrology tools for various sectors.

IQE has taken a 100% ownership in its CSDC joint venture in Singapore. The venture provides compound semiconductor technologies using molecular beam epitaxy (MBE) tools.

Brewer Science will host a Manufacturing Day Exhibition and Job Fair on Oct 17. The event will include Brewer and other regional manufacturers. It will be held at Brewer Science in Rolla, MO.

Chipmakers and OEMs
TSMC has announced that its N7+ process, based on extreme ultraviolet (EUV) lithography technology, is in high-volume production. “N7+, which began volume production in the second quarter of 2019, is matching yields similar to the original N7 process that has been in volume production for more than one year,” according to TSMC.

Samsung posted mixed results in the quarter. Here’s a summary from Bloomberg.

GlobalFoundries has acquired the PDK (process design kit) engineering team from Smartcom Bulgaria. The group will expand GF’s PDK efforts. Since 2015, Smartcom has supported GF’s PDK development spanning from 350nm to 12nm.

Qorvo has acquired Cavendish Kinetics, a supplier of high-performance RF MEMS technology for antenna tuning applications. Separately, Dialog Semiconductor has signed a definitive agreement to acquire Creative Chips GmbH, a supplier of chips for the Industrial Internet of Things (IIoT) market.

The U.S. Supreme Court snubbed the University of Wisconsin’s appeal in a patent fight with Apple, according to a report from Reuters.

Packaging
IEEE has released the 2019 Heterogeneous Integration Roadmap (HIR). The roadmap maps out the future of electronics, identifying technology requirements and potential solutions. It also delivers a 25-year projection for heterogeneous integration of emerging devices and materials.

Jiangsu Changjiang Electronics Technology (JCET) recently announced the appointment of Zheng Li as chief executive and a director. Li replaces Choon Heung Lee as chief executive. Lee will continue to serve as chief technology officer.

Events
Find upcoming semiconductor industry events here. For example, the 65th annual IEDM conference will be held from Dec. 7-11 in San Francisco. Sponsored by the IEEE Electron Devices Society, IEDM consists of a plethora of presentations. Among them are:

*TSMC will describe its 5nm platform. The process offers nearly twice the logic density (1.84x) and a 15% speed gain or a 30% power reduction over 7nm. It incorporates extensive use of EUV lithography.

*Intel will describe a monolithic-like 3D technology. In the technology, Intel fabricates finFET transistors on a silicon wafer. On a separate wafer, Intel fabricates a germanium (Ge) film for use as a buffer layer. “They flipped the second wafer, bonded it to the first, annealed them both to produce a void-free interface, cleaved the second wafer away except for the Ge layer, and then built gate-all-around Ge-channel PMOS devices on top of it,” according to an abstract.

*Imec will describe p- and n-type vertical gate-all-around nanowire and nanosheet transistors with SiGe/silicon pillars and self-aligned spacers.

*CEA-Leti will describe a spiking neural network on a chip. “CEA-Leti built a 130nm CMOS test chip with analog neurons and resistive-RAM-based (RRAM) synapses, monolithically integrated on top of CMOS devices,” according to an abstract.



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